Semiconductor device

ABSTRACT

A recording layer  52  made of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layer  52   a  positioned on a lower electrode TP side of the recording layer  52  is higher than the corresponding concentration of a second layer  52   b  positioned on an upper electrode  53  side. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

TECHNICAL FIELD

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a technique effectivelyapplied to a semiconductor device provided with a memory elementincluding a phase-change material.

BACKGROUND ARTECTS OF THE INVENTION

As a recording technique using physics of a chalcogenide material, aphase-change memory and a phase-change optical disc are cited. As aphase-change material used for the phase-change memory and thephase-change optical disc, a chalcogenide material containing Te(tellurium) is known.

U.S. Pat. No. 5,254,382 (patent document 1) has disclosed an opticaldisc medium using a chalcogenide material expressed as{(Ge_(y)Te_(1-y))_(a)(Sb_(z)Te_(1-z))_(1-a)}_(1-b)(In_(1-x)Te_(x))_(b)(Here, 0.4≦y≦0.6, 0.3≦z≦0.6, 0.4≦z≦0.6, 0.1≦b≦0.3) as a recording layer.In this case, for the purpose of improving the stability of an amorphousstate while maintaining a characteristic of being able to crystallizerapidly and improving long-term data storage stability, In is added toGe—Sb—Te.

On the other hand, in U.S. Pat. No. 5,883,827 (patent document 2), anon-volatile memory using a chalcogenide material film has beendescribed in detail. This non-volatile memory is a phase-change memoryin which stored information is written by the change in atomicarrangement of a phase-change material film in accordance with Jouleheat and cooling rate caused by a current flowing in the phase-changematerial film itself. For example, since a phase-change material film isonce molten by applying heat of higher than 600° C. in Joule heat whenforming a noncrystalline (amorphous) state, the operation current tendsto be large, and a resistance value changes by two to three orders ofmagnitude in accordance with the crystalline state.

As for the electrical phase-change memory, studies for that usingGe₂Sb₂Te₅ have been promoted mainly. For example, Japanese PatentApplication Laid-Open Publication No. 2002-109797 (patent document 3)has disclosed a recording element using GeSbTe. Also, Japanese PatentApplication Laid-Open Publication No. 2003-100991 (patent document 4)has disclosed a technique related to a memory using a chalcogenidematerial. Moreover, a non-patent document 1 has revealed that aphase-change memory using a phase-change film made of Ge₂Sb₂Te₅ isrewritable 10¹² times. Further, a non-patent document 2 has disclosed atechnique related to a phase-change memory using a crystal-growthmaterial.

Patent Document 1: U.S. Pat. No. 5,254,382

Patent Document 2: U.S. Pat. No. 5,883,827

Patent Document 3: Japanese Patent Application Laid-Open Publication No.2002-109797

Patent Document 4: Japanese Patent Application Laid-Open Publication No.2003-100991

Non-Patent Document 1: IEEE International Electron Devices meeting,TECHNICAL DIGEST, 2001, pp. 803-806

Non-Patent Document 2: Nature Materials, Vol. 4, 2005, pp. 347-351

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention

For example, according to a memory configuration of FIG. 12 in U.S. Pat.No. 5,883,827 (patent document 1), the memory includes a memory cellarray, a row decoder XDEC, a bit (column) decoder YDEC, a reader circuitRC, and a writer circuit WC. In the memory cell array, memory cells MCprare disposed at each of the intersections of word lines WLp (p=1, . . ., n) and data lines DLr (r=1, . . . , m). Each memory cell has aconfiguration in which a memory element RM′ and a select transistor QMconnected in series are interposed between a bit line DL and groundpotential. The word line WL is connected to a gate of the selecttransistor, and a bit select line YSr (r=1, . . . , m) is connected to acorresponding bit select switch QAr, respectively.

In the configuration as mentioned above, when the select transistor onthe word line selected by the row decoder XDEC is conducted and the bitselect switch corresponding to the bit select line selected by the bitdecoder YDEC is conducted, a current path is formed in the select memorycell, and a read signal is generated to a common bit line I/O. Since theresistance value in the select memory cell differs depending on thestored information, the voltage output to the common bit line I/Odiffers depending on the stored information. By specifying thedifference by the reader circuit RC, the stored information of theselect memory cell is read.

In such a phase-change memory, a phase-change material used in anoptical disc as well is used as a recording layer, but different from anoptical disc, in the phase-change memory, resistance to high temperatureis sometimes required in a manufacturing process and use environmentthereof. However, for example, when a memory is configured with using astandard phase-change material such as Ge₂Sb₂Te₅ as a recording layer,there are the following problems for usage at high temperature.

The first problem is instability of the amorphous state. That is, sincethe amorphous state is a metastable phase, crystallization is rapidlyprogressed in a high temperature environment. For example, amicrocomputer for controlling an automobile is required to have aresistance to a usage in a high temperature environment of about 140° C.However, when Ge₂Sb₂Te₅ is used as a recording layer, an amorphous stateis changed to a crystalline state, that is, to a low-resistance state ina few hours, and therefore, data retention property is insufficient insuch a high temperature environment and is not suitable for use.

Also, in a microcomputer mounted with a memory, a memory element isexposed to a high temperature environment for soldering andcompression-bonding of the chip in a process of packaging amicrocomputer chip. In the case of the microcomputer, packaging isgenerally performed after recording a program to the memory portion.However, in a memory whose data is erased at a high temperatureenvironment in the packaging process, data has to be written after thepackaging, and a process different from usual has to be taken. Sinceheat load in several minutes at 250° C. for soldering and in severalhours at 180° C. for compression-bonding is applied, data retentionproperty in a higher temperature environment than an operatingtemperature has to be secured even for a short period. Therefore, anon-volatile memory for a microcomputer has to be provided with dataretention property resistant to such a heat load in a manufacturingprocess, and much stricter heat-resistance than that of an optical discis required.

The second problem is a resistance value in an amorphous state at hightemperature. Since chalcogenide containing Te (tellurium) as a maincomponent is a semiconductor whose band gap is narrow, a resistancethereof is generally lowered in an exponential manner as the temperaturebecomes higher. Since a degree of the change is larger in an amorphousstate than in a crystalline state, even if there is a large resistanceratio at room temperature, the resistance ratio is lowered when thetemperature is increased to 100° C. or higher, and therefore, therearises a problem that reading margin cannot be taken. For example, inthe case of Ge₂Sb₂Te₅, a ratio of reset resistance/set resistance atroom temperature is about 100 times. However, under the condition of100° C. or higher, the reset resistance is significantly decreased, andthe ratio is decreased to about 30 times. Therefore, a large readingmargin which is an advantage of a phase-change memory cannot be taken,and depending on cases, a reading method has to be changed in accordancewith an environment temperature.

As described above, some problems have occurred in a memory using thephase-change material. In particular, since the above-described secondproblem regarding the resistance value at high temperature is unique toan electrical memory using a chalcogenide material, this problem is notconsidered for the chalcogenide material for an optical recordingmedium. Therefore, a phase-change memory element using a chalcogenidematerial having an appropriate resistance value and capable of realizingstable data retention property even in a use environment and amanufacturing process at high temperature is required.

On the other hand, for improving data retention property (that is, heatresistance) in a high temperature state as described above, an additionof indium (In) to a composition of a phase-change memory element isconsidered. FIG. 35 is an explanatory diagram schematically showing across-sectional configuration example around a phase-change memoryelement and a problem thereof in a semiconductor device studied as apremise of the present invention. In FIG. 35, for example, on a plug 43(lower electrode TP) including a main conductor film 43 b of tungsten(W) and a conductive barrier film 43 a of titanium (Ti)/titanium nitride(TiN), a memory element RM′ is formed. The memory element RM′ includes,for example, an interface layer 51 made of tantalum oxide (for example,Ta₂O₅), a recording layer 520 made of a chalcogenide layer with auniform composition of In—Ge—Sb—Te, and an upper electrode 53 made oftungsten. In this manner, by adding indium (In) to a chalcogenide layerand providing the interface layer 51 of oxide or nitride such as Ta₂O₅,heat resistance can be improved. More specifically, an unintentionalchange from an amorphous state to a crystalline state at hightemperature can be prevented.

In such a phase-change memory element, a shape of the lower electrode TPis different from that of the upper electrode 53 in most cases.Generally, temperature of an electrode side whose contact area to achalcogenide layer is smaller (that is, lower electrode TP side) tendsto be increased, and therefore, an electrode side whose contact area islarger (that is, upper electrode 53 side) is not molten at the time ofreset, or even if it is molten, it is recrystallized during coolingthereof to crystallize. Amorphization occurs around the electrode sidewhose contact area is smaller (lower electrode TP), and a region A1which is crystallized during a manufacturing process and remains in acrystalline state is present on an outer side thereof. Note that aregion A2 is a region which is crystallized at the time of set and isamorphized at the time of reset. Also, a contact in this specificationincludes not only the direct contact, but also the contact withinterposing a layer or a region such as an insulator or semiconductorwhich is thin enough to allow the current to flow.

The shortest distance between the lower electrode TP and a closestcrystallized region A1 differs depending on the intensity and time ofthe current flowing at the time of reset. When an area of a transistorspecifying an element is reduced, a current is reduced, and a distanceL1 between the lower electrode TP and the closest crystallized region A1in a film surface direction of a chalcogenide layer becomes smaller thana distance L2 in a film thickness direction between the lower electrodeTP and the upper electrode 53 (or distance between the lower electrodeTP and crystallized region A1 in front of the upper electrode).Therefore, there is a possibility that a lot of current flows in theclosest gap (that is, the film surface direction) at the time of set.However, the closest gap becomes unstable due to a process variation, aprocess failure and others of the recording layer 520. Consequently,there is a possibility that failures such as a characteristic variationbetween elements and reduction in the number of rewritable times arecaused.

Also, since there is a possibility that an atomic arrangement of therecording layer 520 is changed at high temperature, a further resistanceincrease resulting therefrom occurs in the recording layer 520, so thata high voltage is required for a next set operation. More specifically,when the region A2 of FIG. 35 is in an amorphous state, if atomicarrangement is changed in the entire region A2 at the time of hightemperature and further resistance increase is caused, the subsequentset operation becomes difficult in some cases.

Further, since a strong electric field is applied in a phase-changememory element, when ions or easily-ionized elements or components existin a film between electrodes, they may be moved by the electric field.More specifically, in FIG. 35, since a resistance of a crystallizedregion A1 from an initial state is low, if In—Ge—Sb—Te has the uniformcomposition in a film thickness direction, the potential gradientbetween an outer edge portion of the lower electrode TP and thecrystallized region A1 from an initial state is largest at the time ofset, and a set operation accompanied with impact ionization is started.At this time, a movement of In ions (positive ions) also tends to occur,and segregation and structure disturbance are caused when temperature isincreased, which becomes the cause of changing the resistance to ahigh-resistance side. Note that, at the time of set/reset operations, ahigh voltage is applied to the upper electrode 53 based on the lowerelectrode TP in general, and therefore, In ions move easily to the lowerelectrode TP side.

As is understood from the foregoing, a phase-change memory elementprovided with high heat resistance and more stable data retentionproperty is required. The present invention has been made inconsideration of that, and the above and other objects and novelcharacteristics of the present invention will be apparent from thedescription of this specification and the accompanying drawings.

Means for Solving the Problems

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

A semiconductor device of the present invention has a structure in whicha recording layer made of a chalcogenide material and disposed betweenan upper electrode and a lower electrode has a two or more layerstructure, and a first layer on the lower electrode side is larger thana second layer on the upper electrode side in average content of a groupII element or a group III element in a film thickness direction. Thefirst layer is made of a material containing, for example, at least oneelement selected from a group including gallium (Ga) and indium (In) of7 atomic % or more and 40 atomic % or less, germanium (Ge) of 5 atomic %or more and 35 atomic % or less, antimony (Sb) of 5 atomic % or more and25 atomic % or less, and tellurium (Te) of 40 atomic % or more and 65atomic % or less. indium (In) is the group III element.

Here, the reason why tellurium (Te) of 40 atomic % or more and 65 atomic% or less is contained is to achieve an appropriate rewriting propertyand data retention property. The reason why germanium (Ge) of 5 atomic %or more and 35 atomic % or less and antimony (Sb) of 5 atomic % or moreand 25 atomic % or less are contained is to achieve the appropriatenumber of rewritable times and current amount required for rewriting.Also, the reason why at least one element which is selected from a groupincluding gallium (Ga) and indium (In) of 7 atomic % or more and 40atomic % or less is contained is to achieve an excellent data retentionproperty and a high resistance ratio.

Further, when the average content of a group II element (for example, Znor Cd) or a group III element (for example, Ga or In) in the first layerin a film thickness direction is set to 7 to 40 atomic %, the averagecontent of a group II or group III element in the second layer in thefilm thickness direction is, for example, 0 to 15 atomic %, and thedifference of the both average contents is set to 5 atomic % or more. Asdescribed above, by forming the recording layer to have two or morelayer structure with different concentrations, the high heat resistanceand a stable data retention property can be realized.

Also, a semiconductor device of the present invention uses such arecording layer as a memory element and is provided with a memorycircuit in which voltage polarity between the upper electrode and thelower electrode can be set in reverse at the set and reset operations.In this manner, since a movement of an ionized element to one directioncan be prevented, the number of rewritable times can be increased and astable data retention property and the like can be realized. Note thatthe memory circuit is desirably configured so that the upper electrodeside becomes positive at the time of set and the lower electrode sidebecomes positive at the time of reset.

Effect of the Invention

The effects obtained by typical aspects of the present invention will bebriefly described. That is, a semiconductor device having high heatresistance and a stable data retention property can be realized.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration example around amemory cell array included in a semiconductor device according to afirst embodiment of the present invention;

FIG. 2 is a layout diagram corresponding to the circuit of FIG. 1;

FIG. 3 is a cross sectional view schematically showing a configurationexample of a main portion in the semiconductor device of FIG. 2;

FIG. 4 is an explanatory diagram schematically showing one example of adetailed configuration around a memory element of FIG. 3 and its effect;

FIG. 5 is an explanatory diagram showing a pulse applied to the memoryelement of FIG. 4, in which FIG. 5A shows an applied pulse shape andFIG. 5B shows temperature change in a recording layer by the appliedpulse;

FIG. 6 is an explanatory diagram schematically showing crystallizationprocess of a chalcogenide material, in which FIG. 6A shows a crystalnucleation type and FIG. 6B shows a crystal growth type;

FIG. 7 is an explanatory diagram showing one example of a compositionrange of the recording layer in FIG. 4;

FIG. 8 is an explanatory diagram showing composition dependency of areset resistance/set resistance ratio of the memory element in FIG. 4;

FIG. 9 is an explanatory diagram showing composition dependency of a setvoltage of the memory element in FIG. 4;

FIG. 10 is an explanatory diagram showing composition dependency of thenumber of rewritable times of the memory element in FIG. 4;

FIG. 11 is an explanatory diagram showing composition dependency of anoperation guaranteed temperature of the memory element in FIG. 4;

FIG. 12 is an explanatory diagram showing another example of acomposition range of the recording layer in FIG. 4;

FIG. 13 is a cross sectional view schematically showing a configurationexample of a main portion in a manufacturing process of thesemiconductor device according to the first embodiment of the presentinvention;

FIG. 14 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.13;

FIG. 15 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.14;

FIG. 16 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.15;

FIG. 17 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.16;

FIG. 18 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.17;

FIG. 19 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.18;

FIG. 20 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.19;

FIG. 21 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.20;

FIG. 22 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.21;

FIG. 23 is a cross sectional view schematically showing thesemiconductor device in the manufacturing process continued from FIG.22;

FIG. 24 is an explanatory diagram showing an activation energy forcrystallization of a recording layer accompanying a manufacturingprocess of a semiconductor device according to a second embodiment ofthe present invention;

FIG. 25 is an explanatory diagram showing a temperature profile insolder reflow process in a semiconductor device according to a thirdembodiment of the present invention;

FIG. 26 is an explanatory diagram showing a data retention property whenpreheat treatment for the solder reflow process of FIG. 25 is performed;

FIG. 27 is a circuit diagram showing a configuration example of asemiconductor device according to a fourth embodiment of the presentinvention;

FIG. 28 is a waveform diagram showing one example of a reading operationin the semiconductor device of FIG. 27;

FIG. 29 is a waveform diagram showing one example of a rewritingoperation in the semiconductor device of FIG. 27;

FIG. 30 is a circuit diagram showing a configuration example of asemiconductor device according to a fifth embodiment of the presentinvention;

FIG. 31 is a circuit diagram showing a detailed configuration example ofa part of a circuit in the semiconductor device of FIG. 30;

FIG. 32 is a waveform diagram showing one example of a rewritingoperation in the semiconductor device of FIG. 30;

FIG. 33 is a circuit diagram showing a configuration example of asemiconductor device according to a sixth embodiment of the presentinvention;

FIG. 34 is a waveform diagram showing one example of a reading operationin the semiconductor device of FIG. 33; and

FIG. 35 is an explanatory diagram schematically showing across-sectional configuration example around a phase-change memoryelement and a problem thereof in a semiconductor device studied as apremise of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the embodiments described below, the invention will be described in aplurality of sections or embodiments when required as a matter ofconvenience. However, these sections or embodiments are not irrelevantto each other unless otherwise stated, and the one relates to the entireor a part of the other as a modification example, details, or asupplementary explanation thereof. Also, in the embodiments describedbelow, when referring to the number of elements (including number ofpieces, values, amount, range, and the like), the number of the elementsis not limited to a specific number unless otherwise stated or exceptthe case where the number is apparently limited to a specific number inprinciple. The number larger or smaller than the specified number isalso applicable.

Further, in the embodiments described below, it goes without saying thatthe components (including element steps) are not always indispensableunless otherwise stated or except the case where the components areapparently indispensable in principle. Similarly, in the embodimentsdescribed below, when the shape of the components, positional relationthereof, and the like are mentioned, the substantially approximate andsimilar shapes and the like are included therein unless otherwise statedor except the case where it can be conceived that they are apparentlyexcluded in principle. The same goes for the numerical value and therange described above.

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference symbolsthroughout the drawings for describing the embodiment, and therepetitive description thereof will be omitted.

First Embodiment

A semiconductor device of the first embodiment has a memory elementincluding a phase-change material, and as described later in FIG. 4 andothers, a structure of the memory element is a main characteristicthereof. In the following, an entire configuration example of asemiconductor device including the memory element will be described.

FIG. 1 is a circuit diagram showing a configuration example around amemory cell array included in a semiconductor device according to afirst embodiment of the present invention. FIG. 2 is a layout diagramcorresponding to the circuit of FIG. 1. In FIGS. 1 and 2, for preventingthe description from being complicated, the illustration of word linesand bit lines which are generally disposed in large numbers issimplified, and four word lines WL1 to WL4 and four bit lines BL1 to BL4are shown. Also, a memory cell array shown in FIGS. 1 and 2 is known asa NOR-type and can perform high-speed reading, and is therefore suitablefor storage of system program and others. Accordingly, the memory cellarray is used for a single memory chip or an embedded logic LSI such asa microcomputer.

In FIG. 1, memory cells MC11 to MC14 are electrically connected to theword line WL1. Similarly, memory cells MC21 to MC24, MC31 to MC34, andMC41 to MC44 are electrically connected to the word lines WL2, WL3 andWL4, respectively. Also, the memory cells MC11, MC21, MC31 and MC41 areelectrically connected to the bit line BL1. Similarly, memory cells MC12to MC42, MC13 to MC43, and MC14 to MC44 are electrically connected tothe bit lines BL2, BL3 and BL4, respectively.

Each of the memory cells MC includes one memory cell transistor QMformed of a MIS (Metal Insulator Semiconductor) transistor and onememory element RM connected in series to the memory cell transistor.Each of the word lines WL is electrically connected to a gate of thememory cell transistor QM constituting each memory cell MC. Each of thebit lines BL is electrically connected to the memory element RMconstituting each memory cell MC. Also, an end of each memory celltransistor QM on a side different from that of the memory element RM iselectrically connected to a source line SL.

The word lines WL1 to WL4 are driven by word drivers WD1 to WD4,respectively. The signal from the X address decoder XDEC determineswhich word drivers WD are to be selected. Here, a reference symbol VPLdenotes a power supply line, Vdd denotes power supply voltage, and VGLdenotes a potential extraction line of each word driver. Note that,here, the potential extraction line VGL is fixed at ground voltage.

One ends of the bit lines BL1 to BL4 are connected to a sense amplifierSA through select transistors QD1 to QD4 formed of MIS transistors. Eachof the select transistors QD is selected in accordance with an addressinput through a Y address decoder YDEC1 or YDEC2. In the configurationof the first embodiment, QD1 and QD2 are selected by YDEC1 and QD3 andQD4 are selected by YDEC2. The sense amplifier SA detects and amplifiesa signal read from the memory cell MC through the select transistor QD.Note that, although not shown in the figure, circuits for providingvoltage or current for reading and writing are connected to each of theselect transistors QD in addition to the sense amplifier SA.

In FIG. 2, a reference symbol FL denotes an active region, M1 denotes afirst layer wiring, M2 denotes a second layer wiring, and FG denotes agate electrode layer used as a gate of a MIS transistor formed on asilicon substrate. Also, a reference symbol FCT denotes a contact holewhich connects between an upper surface of the active region FL and alower surface of the first layer wiring M1, SCT denotes a contact holewhich connects between an upper surface of the first layer wiring M1 anda lower surface of the memory element RM, and TCT denotes a contact holewhich connects between an upper surface of the first layer wiring M1 anda lower surface of the second layer wiring M2.

The memory element RM is extended to the second layer wiring M2 throughthe contact hole TCT between the memory cells electrically connected tothe same bit line. The second layer wiring M2 is used as the bit linesBL. The word lines WL1 to WL4 are formed from a gate electrode layer FG.A stacked layer of polysilicon and silicide (alloy of silicon and highmelting point metal) or the like is used for the gate electrode layerFG. Also, for example, the memory cell transistor QM1 constituting thememory cell MC11 shares a source region with the memory cell transistorQM2 constituting the memory cell MC21, and the source region isconnected to a source line SL serving as the first layer wiring M1through a contact hole.

The bit lines BL1 to BL4 are connected to source sides of the selecttransistors QD1 to QD4 disposed in the periphery of the memory cellarray. The select transistors QD1 and QD2 share a drain region, and theselect transistors QD3 and QD4 share a drain region. These selecttransistors QD have a function to select a specified bit line uponreception of a signal from the Y address decoder YDEC1 or YDEC2. Notethat, for example, the select transistors QD are of n-channel type inthe first embodiment.

FIG. 3 is a cross sectional view schematically showing a configurationexample of a main portion in the semiconductor device of FIG. 2. In FIG.3, a cross sectional configuration of a main portion of a memory cellregion MARE and a logic circuit region LARE is shown schematically. Inthe memory cell region MARE, the memory cells MC including the memorycell transistor QM as shown in FIG. 2 are arranged in an array. In thelogic circuit region LARE, for example, several types of memoryperipheral circuits including the sense amplifier as shown in FIG. 2 andthe like are disposed, and a plurality of several types of logiccircuits are additionally disposed in the case of a semiconductor devicein which a logic and a memory are disposed in combination. Note that, inFIG. 3, for the simplification of the understanding, the memory cellregion MARE and the logic circuit region LARE are shown next to eachother. However, a positional relation of the memory cell region MARE andthe logic circuit region LARE in a cross section can be modifiedaccording to need.

As shown in FIG. 3, for example, element isolation regions 12 are formedon a main surface of a semiconductor substrate (semiconductor wafer) 11made of a p-type single crystal silicon, and p-type wells 13 a and 13 band a n-type well 14 are formed in the active regions isolated by theelement isolation regions 12. Of these, the p-type well 13 a is formedin the memory cell region MARE, and the p-type well 13 b and the n-typewell 14 are formed in the logic circuit region LARE. On the p-type well13 a in the memory cell region MARE, memory cell transistors QM1 and QM2formed of n-channel type MIS transistors are formed. On the p-type well13 b in the logic circuit region LARE, a n-channel type MIS transistorQN is formed, and on the n-type well 14 in the logic circuit regionLARE, a p-channel type MIS transistor QP is formed.

The memory cell transistors QM1 and QM2 are formed separately from eachother on the p-type well 13 a, and each of them has a gate insulator 15a on a surface of the p-type well 13 a and the gate electrode 16 a on agate insulator 15 a. On a sidewall of the gate electrode 16 a, asidewall (sidewall spacer) 18 a made of a silicon oxide film, a siliconnitride film, or a stacked film thereof is formed. In the p-type well 13a, a semiconductor region (n-type impurity diffused layer) DN3 servingas a drain region of QM1, a semiconductor region (n-type impuritydiffused layer) DN4 serving as a drain region of QM2, and asemiconductor region (n-type impurity diffused layer) DNC serving as asource region of QM1 and QM2 are formed.

Each of the semiconductor regions DN3, DN4 and DNC has LDD (LightlyDoped Drain) structure and is composed of a n⁻-type semiconductor region17 a and a n⁺-type semiconductor region 19 a whose impurityconcentration is higher than that of the semiconductor region 17 a. Then⁻-type semiconductor region 17 a is formed in the p-type well 13 aunder the sidewall 18 a, the n⁺-type semiconductor region 19 a is formedin the p-type well 13 a outside the gate electrode 16 a and the sidewall18 a, and the n⁺-type semiconductor region 19 a is formed in the p-typewell 13 a at a position apart from a channel region by a width of then⁻-type semiconductor region 17 a. The semiconductor region DNC is acommon source region shared by the memory cell transistors QM1 and QM2next to each other formed in the same element active region.

The MIS transistor QN formed in the logic circuit region LARE has almostthe same configuration as those of QM1 and QM2. More specifically, QNincludes a gate insulator 15 b on a surface of the p-type well 13 b anda gate electrode 16 b on the gate insulator 15 b, and a sidewall(sidewall spacer) 18 b made of silicon oxide or the like is formed on asidewall of the gate electrode 16 b. A n⁻-type semiconductor region 17 bis formed in the p-type well 13 b under the sidewall 18 b, and a n⁺-typesemiconductor region 19 b whose impurity concentration is higher thanthat of the n⁻-type semiconductor region 17 b is formed outside then⁻-type semiconductor region 17 b. By the n⁻-type semiconductor region17 b and the n⁺-type semiconductor region 19 b, source-drain regions(semiconductor region) DN1 and DN2 having a LDD structure of QN areformed.

The MIS transistor QP formed in the logic circuit region LARE includes agate insulator 15 c on a surface of the n-type well 14 and a gateelectrode 16 c on the gate insulator 15 c, and a sidewall (sidewallspacer) 18 c made of silicon oxide or the like is formed on a sidewallof the gate electrode 16 c. A p⁻-type semiconductor region 17 c isformed in the n-type well 14 under the sidewall 18 c, and a p⁺-typesemiconductor region 19 c whose impurity concentration is higher thanthat of the p⁻-type semiconductor region 17 c is formed outside thep⁻-type semiconductor region 17 c. By the p⁻-type semiconductor region17 c and the p⁺-type semiconductor region 19 c, source-drain regions(semiconductor region) DP1 and DP2 having a LDD structure of QP areformed.

A metal silicide layer (for example, cobalt silicide (CoSi₂) layer) 25is formed on each surface of the gate electrodes 16 a, 16 b and 16 c,the n⁺-type semiconductor regions 19 a and 19 b and the p⁺-typesemiconductor region 19 c. By this means, the reduction of diffusionresistance and contact resistance of the n⁺-type semiconductor regions19 a and 19 b and the p⁺-type semiconductor region 19 c can be achieved.

On the semiconductor substrate 11, an insulator (interlayer insulatingfilm) 31 is formed so as to cover the gate electrodes 16 a, 16 b and 16c. The insulator 31 is made of, for example, a silicon oxide film or thelike, and an upper surface of the insulator 31 is flatly formed so thatthe insulator 31 has almost the same height in the memory cell regionMARE and the logic circuit region LAKE. Contact holes (opening portion,connection hole) are formed in the insulator 31, and plugs (contactelectrode) 33 are formed in the contact holes. The plug 33 is formedfrom a conductive barrier film 33 a made of a titanium film, a titaniumnitride film or a stacked film thereof formed on a bottom portion and asidewall of the contact hole and a tungsten (W) film (main conductorfilm) 33 b formed on the conductive barrier film 33 a so as to fill theinside of the contact hole. The contact hole and the plug 33 are formedon the semiconductor regions DN1 to DN4, DNC, DP1 and DP2, and thoughnot shown in the figure, on the gate electrodes 16 a, 16 b and 16 c.

On the insulator 31 in which the plugs 33 are embedded, an insulator 34made of, for example, a silicon oxide film is formed, and a wiring(first wiring layer) M1 serving as a first layer wiring is formed in awiring trench (opening portion) formed in the insulator 34. The wiringM1 is formed from a conductive barrier film 36 a made of a titaniumfilm, a titanium nitride film or a stacked film thereof formed on abottom portion and a sidewall of the wiring trench and a main conductorfilm 36 b made of a tungsten (W) film formed on the conductive barrierfilm 36 a so as to fill the inside of the wiring trench. The wirings M1are electrically connected through the plugs 33 to the semiconductorregions DN1 to DN4, DNC, DP1 and DP2 and the gate electrodes 16 a, 16 band 16 c and others. In the memory cell region MARE, the wiring M1connected through the plug 33 to the semiconductor region DNC for asource of QM1 and QM2 is the source line SL.

On the insulator 34 in which the wirings M1 are embedded, an insulator(interlayer insulating film) 41 made of, for example, a silicon oxidefilm is formed. In the memory cell region MARE, through holes (openingportion, connection hole) are formed in the insulator 41, and plugs(contact electrode) 43 are formed in the through holes. The plug 43 isformed from a conductive barrier film 43 a made of a titanium film, atitanium nitride film or a stacked film thereof formed on a bottomportion and a sidewall of the through hole and a tungsten (W) film (mainconductor film) 43 b formed on the conductive barrier film 43 a so as tofill the inside of the through hole. The plug 43 is connected to thememory element RM described later and functions as the lower electrodeTP thereof. The through holes and the plugs 43 (lower electrode TP) areformed on the wirings M1 connected through the plugs 33 to thesemiconductor regions DN3 and DN4 for the drains of QM1 and QM2 in thememory cell region MARE, and are electrically connected thereto.

In the memory cell region MARE, on the insulator 41 in which the plugs43 are embedded, the memory elements RM formed from a peeling-preventingfilm (interface layer) 51, a recording layer (phase-change film,chalcogenide layer) 52 on the peeling-preventing film 51 and an upperelectrode film (upper electrode) 53 on the recording layer 52 areformed. More specifically, the memory element RM is formed from astacked pattern including the peeling-preventing film 51, the recordinglayer 52 and the upper electrode film 53.

The peeling-preventing film 51 is interposed between the insulator 41 inwhich the plugs 43 are embedded and the recording layer 52 and has afunction to improve the adhesion (adhesiveness) therebetween and toprevent the recording layer 52 from being peeled off. Also, thepeeling-preventing film 51 can function as a resistive layer for heatgeneration to heat the recording layer 52. The peeling-preventing film51 is made of, for example, tantalum oxide or the like (for example,Ta₂O₅), and a film thickness thereof can be, for example, about 0.5 to 5nm. Note that the peeling-preventing film 51 is desired to be formed,but depending on a case, the formation thereof can be omitted. In thiscase, the recording layer 52 is directly formed on the insulator 41 inwhich the plugs 43 are embedded.

The recording layer 52 can make a transition between two states(phase-change) such as a crystalline state and an amorphous state andhas a function to store information by using a difference in resistancevalue between the two states. The recording layer 52 is made of, forexample, a phase-change material (chalcogenide) including at leasteither indium (In) or gallium (Ga), germanium (Ge), antimony (Sb), andtellurium (Te) with an appropriate composition ratio. Although a detailis described later, in this recording layer 52, for example, aconcentration of indium (In) (or gallium (Ga)) is different between theupper electrode 53 side and the lower electrode TP side.

The upper electrode 53 is made of a conductor film such as a metal filmand is formed from a tungsten (W) film, a tungsten alloy film or thelike, and a film thickness thereof can be, for example, about 50 to 200nm. The upper electrode film 53 has a function to reduce a contactresistance between a plug 64 described later and the recording layer 52and to prevent the recording layer 52 from sublimating when a conductivebarrier film 67 a is formed after forming a through hole for the plug64.

Lower portions of the memory elements RM (lower surface of thepeeling-preventing film 51) are electrically connected to the plugs 43and are electrically connected through the plugs 43, the wirings M1 andthe plugs 33 to the drain regions DN3 and DN4 of the memory celltransistors QM1 and QM2 in the memory cell region MARE. Therefore, theplug 43 is electrically connected to a lower surface side of therecording layer 52.

Also, on the insulator 41, an insulator 61 and an insulator (interlayerinsulating film) 62 on the insulator 61 are formed so as to cover thememory elements RM. More specifically, the insulator 61 is formed on anupper surface of the upper electrode film 53, a sidewall of therecording film 52 and others, and the insulator 62 is formed as theinterlayer insulating film on the insulator 61. A film thickness of theinsulator 61 is smaller than that of the insulator 62 (for example,about several hundreds nm) and can be, for example, about 5 to 20 nm.The insulator 61 is made of, for example, a silicon nitride film, andthe insulator 62 is made of, for example, a silicon oxide film. An uppersurface of the insulator 62 is flatly formed so that the insulator 62has almost the same height in the memory cell region MARE and the logiccircuit region LARE.

In the memory cell region MARE, through holes (opening portion,connection hole) are formed in the insulators 61 and 62, and at least apart of the upper electrode film 53 of the memory element RM is exposedon a bottom portion of the through holes and plugs (contact electrode)64 are formed in the through holes. The plug 64 is formed from aconductive barrier film 67 a made of a titanium film, a titanium nitridefilm or a stacked film thereof formed on a bottom portion and a sidewallof the through hole and a tungsten (W) film (main conductor film) 67 bformed on the conductive barrier film 67 a so as to fill the inside ofthe through hole 63. An aluminum film or the like can be used instead ofthe tungsten film 67 b. The through holes and the plugs 64 are formed onupper portions of the memory elements RM, and the plugs 64 areelectrically connected to the upper electrode films 53 of the memoryelements RM.

Also, in the logic circuit region LARE, a through hole (opening portion,connection hole) is formed in the insulators 41, 61 and 62, and an uppersurface of the wiring M1 is exposed on a bottom portion of the throughhole, and a plug (contact electrode) 66 is formed in the through hole.The plug 66 is formed from a conductive barrier film 67 a made of atitanium film, a titanium nitride film or staked film thereof formed ona bottom portion and a sidewall of the through hole and a tungsten (W)film (main conductor film) 67 b formed on the conductive barrier film 67a so as to fill the inside of the through hole. The through hole and theplug 66 are electrically connected to the wiring M1.

On the insulator 62 in which the plugs 64 and 66 are embedded, wiringsM2 (second wiring layer) serving as a second layer wiring are formed.The wiring M2 is formed from, for example, a conductive barrier film 71a made of a titanium film, a titanium nitride film or stacked filmthereof and an aluminum (Al) film or an aluminum alloy film (mainconductor film) 71 b on the conductive barrier film 71 a. Alternatively,a conductive barrier film similar to the conductive barrier film 71 amay be formed on the aluminum alloy film 71 b to form the wiring M2.

Here, the wiring M2 in the memory cell region MARE is a bit line BL, andthe BL is electrically connected through the plugs 64 to the upperelectrode films 53 of the memory elements RM. Therefore, the wiring M2constituting the bit line BL in the memory cell region MARE iselectrically connected through the plugs 64, the memory elements RM, theplugs 43, the wirings M1 and the plugs 33 to the drain regions DN3 andDN4 of the memory cell transistors QM1 and QM2.

Further, in the logic circuit region LARE, the wiring M2 is electricallyconnected through the plug 66 to the wiring M1, and further through theplugs 33 to the semiconductor region DN1 of the MIS transistor QN andthe semiconductor region DP2 of the MIS transistor QP. Note that aninsulator (not shown) serving as an interlayer insulating film is formedon the insulator 62 so as to cover the wirings M2, and upper wiringlayers (wirings of third and subsequent layers) and others are formedthereon. However, the illustration and description thereof are omittedhere.

In such a configuration, the memory cell of a phase-change memory isconstituted of the memory elements RM and the memory cell transistorsQM1 and QM2 connected thereto. The gate electrode 16 a of each of theQM1 and QM2 is electrically connected to the word line WL (correspondingto word lines WL1 to WL4 in FIG. 2). One end of the memory element RM iselectrically connected through the plug 64 to the bit line formed fromthe wiring M2 (corresponding to bit lines BL1 to BL4 in FIG. 2). Theother end of the memory element RM is electrically connected through theplug 43 (lower electrode TP), the wiring M1, and the plug 33 to thesemiconductor regions DN3 and DN4 for drains of the QM1 and QM2.Further, the semiconductor region DNC for drain of the QM1 and QM2 iselectrically connected through the plug 33 to the source line SL of FIG.2.

Note that the case where n-channel type MIS transistors are used for thememory cell transistors QM1 and QM2 of the phase-change memory has beendescribed in the present embodiment. However, other field effecttransistors such as p-channel type MIS transistors can be used instead.However, as memory cell transistors of a phase change memory, MIStransistors are preferably used in view of high integration, andn-channel type MIS transistors are more suitable compared with p-channeltype MISFETs because n-channel type MIS transistors have a lower channelresistance in an ON state.

FIG. 4 is an explanatory diagram schematically showing an example of adetailed configuration around the memory element of FIG. 3 and an effectthereof. FIG. 5 is an explanatory diagram showing a pulse applied to thememory element of FIG. 4, and FIG. 5A shows an applied pulse shape andFIG. 5B shows temperature change in a recording layer by the appliedpulse. As shown in FIG. 4, the memory element RM includes the recordinglayer (chalcogenide layer) 52 which stores information by causing achange in atomic arrangement, the upper electrode 53 formed on an uppersurface of the recording layer 52, and the peeling-preventing film 51formed below the recording layer 52. Also, the plug 43 (lower electrodeTP) is connected to a lower surface of the peeling-preventing film 51 inthe memory element RM.

As described with reference to FIG. 3, the upper electrode 53 is madeof, for example, tungsten (W), and the peeling-preventing film 51 ismade of, for example, tantalum oxide (for example, Ta₂O₅). Also, thelower electrode TP is formed from the conductive barrier film 43 a andthe main conductor film 43 b, and the conductive barrier film 43 a ismade of, for example, a stacked film of titanium (Ti)/titanium nitride(TiN), and the main conductor film 43 b is made of, for example,tungsten (W) or the like.

The recording layer 52 is made of, for example, a phase-change material(chalcogenide) containing at least either indium (In) or gallium (Ga),germanium (Ge), antimony (Sb), and tellurium (Te) with an appropriatecomposition ratio. Here, the recording layer 52 has a characteristicthat a concentration of indium (In) (or gallium (Ga)) on the lowerelectrode TP side is higher than that on the upper electrode 53 side. Asone example thereof, the recording layer 52 is formed to have a twolayer structure, in which a first layer 52 a on the lower electrode TPside is formed of a film having a high indium (In) concentration and asecond layer 52 b on the upper electrode 53 side stacked on the firstlayer 52 a is formed of a film having an indium (In) concentration lowerthan that of the first layer 52 a (or a film to which no indium (In) isadded).

Note that the recording layer 52 is not limited to the two layerstructure, and it may have more layer structure, that is, n (≧2) layerstructure. In this case, from the lower electrode TP side to the upperelectrode 53 side, a first layer, . . . , a (n−1)-th layer, and a n-thlayer are sequentially formed, and the concentration of indium (In) orothers of the (n−1)-th layer is higher than that of the n-th layer.Alternatively, the recording layer 52 may have the structure that theconcentration of indium (In) or others may be continuously loweredtoward the upper electrode 53 side. In other words, this state isequivalent to the case where the n described above is quite large.Further, the group III element described above (indium (In) or gallium(Ga)) can be replaced with a group II element such as zinc (Zn) orcadmium (Cd) depending on cases.

In order for the recording layer 52 to make transition to a crystallinestate (low-resistance state) or an amorphous state (high-resistancestate), a reset pulse corresponding to the high-resistance state or aset pulse corresponding to the low-resistance state is applied(supplied) to the recording layer 52 through the lower electrode TP.Then, a chalcogenide material is heated by resultant Joule heat, so thatatomic arrangement thereof is changed to be in a crystalline state or anamorphous state, thereby storing information. Note that an applied pulsegenerally has a specification in which the set pulse is longer in timeand lower in voltage or current than the reset pulse as shown in FIG.5A.

When the reset pulse is applied to form a high-resistance state, achalcogenide material is heated to its melting point Tm or higher byJoule heat to be in a molten state. After stopping the pulseapplication, the molten chalcogenide material is rapidly cooled. Asshown in the temperature change of the chalcogenide material at thistime, when a cooling rate after stopping the pulse application issufficiently large, a random atomic arrangement in liquid state isfrozen, and a region except the region A3 including the regions A4 andA5 of FIG. 4 becomes an amorphous state. Note that, similar to theregion A1 described in FIG. 35, the region A3 is a crystallized regionfrom an initial state. In the amorphous state, the recording layer 52has high resistance, and the memory element RM is in a high-resistancestate.

On the other hand, when the set pulse is applied to form alow-resistance state and a chalcogenide material is heated to itscrystallization temperature Tc or higher by Joule heat and retained fora certain period as shown in FIG. 5B, the region including the regionsA4 and A5 in an amorphous state becomes a crystalline state. At thistime, in a configuration example of FIG. 4, since a concentration ofindium (In) is low in the second layer 52 b, the atomic arrangementchange (crystallization) occurs also in the region A4 therein at anearly stage in time series. Further, in the recording layer 52, theatomic arrangement change (crystallization) occurs so as to expand fromthe region A5 on the lower electrode TP side where heat generationeasily occurs to the upper electrode 53 side (so as to be connected tothe region A4). In this crystalline state, the recording layer 52 has alow resistance compared with an amorphous state, and the memory elementRM is in a low-resistance state.

Note that, when multicomponent crystals are minute and have differentcompositions from each other like in the recording layer 520 of FIG. 35described above, a large disturbance of the atomic arrangement occurs attheir interface, so that the resistance value in the crystalline statebecomes relatively higher than that in the amorphous state in somecases. However, since the region A4 in the second layer 52 b is formedwith relatively large crystal grains in the configuration example ofFIG. 4, such a situation hardly occurs.

By supplying a current (by applying a pulse) to the memory element RM tochange the atomic arrangement of the chalcogenide material in thismanner, information can be recorded. In the reading of the recordedinformation, a voltage or current at a level lower than that of the setpulse or reset pulse is applied so as not to change the state of thechalcogenide material, thereby reading the resistance value of thememory element RM. The resistance at the time of reset (high-resistancestate) is higher than that at the time of set (low-resistance state),and the ratio thereof is, for example, 10 to 1 to 1000 to 1 or more.

As described above, by changing the concentration of indium (In) in therecording layer 52 as shown in FIG. 4, for example, the followingeffects can be obtained. First, since the concentration of indium (In)on the upper electrode 53 side is low, at the time of set,crystallization occurs also in the region A4 in addition to the regionA5 at an early stage in time series. Therefore, at the time of set,current flows easily between the regions A5 and A4 closest to each other(that is, in film thickness direction (longitudinal direction)), so thata failure caused by the current flowing in a film surface direction(horizontal direction) as described in FIG. 35 can be reduced, and astable data retention property can be realized.

Also, as described in FIG. 35, the further resistance increase occurs athigh temperature due to the change in the atomic arrangement of therecording layer, and there is a possibility that a next set operation isaffected. However, in the configuration example of FIG. 4, a portionwhere the change of the atomic arrangement occurs easily is limited tothe first layer 52 a whose indium (In) concentration is high. Therefore,even if the atomic arrangement is changed at this portion of the firstlayer 52 a, since the region itself is smaller compared with the case ofFIG. 35 and the region is on the lower electrode TP side which is heatedeasily at the time of set, the next set operation is not affected somuch. Further, in the transition from an amorphous state to acrystalline state, since the region A4 is crystallized early and thusthe resistance value is decreased early compared with the case of FIG.35, the application of high voltage for a relatively long time betweenthe upper electrode 53 and the lower electrode TP can be prevented.Therefore, movement of In ions (positive ion) ION1 is hard to occur, andthe occurrence of resistance increase due to the segregation andstructure disturbance can be suppressed.

In the manner as described above, a stable data retention property canbe realized. Also, since indium (In) is added to the first layer 52 a ofthe recording layer 52, even if the second layer 52 b is crystallized athigh temperature, the first layer 52 a can maintain its amorphous state.Therefore, the upper electrode 53 and the lower electrode TP are notconnected by low resistance, thereby being able to realize highheat-resistance property.

Next, the mechanism of the occurrence of a phase change in thechalcogenide material will be described with reference to FIG. 6. FIG. 6is an explanatory diagram schematically showing the crystallizationprocess of the chalcogenide material, in which FIG. 6A shows a crystalnucleation type and FIG. 6B shows a crystal growth type.

The crystal nucleation type shown in FIG. 6A is a type of a material inwhich many crystal nuclei are generated though the growth rate thereofis slow and many crystal grains are generated therefrom. Typicalexamples of the crystal-nucleation-type material include a materialbased on a pseudo-binary-system composition of GeTe—Sb₂Te₃ such asGe₂Sb₂Te₅. On the other hand, in the crystal growth type shown in FIG.6B, new crystal nuclei are hardly generated and crystal grains areextended from the crystalline region near the amorphous region becauseof the high crystal growth rate, whereby crystallization proceeds. Thematerials belonging to this crystal growth type are based on a Sb₇₀Te₃₀eutectic material, and include Ag—In—Sb—Te, for example. Although boththe crystal nucleation type and the crystal growth type include Sb(antimony) and Te (tellurium), the former contains Te as a maincomponent and the latter contains Sb as a main component, and thecrystallization mechanism significantly differs by this difference incomposition.

Since the physics of a phase-change material determines a property as amemory in a phase-change memory and a phase-change optical disc, a lotof inventions for improving the material physics have been disclosedbefore. The Ag—In—Sb—Te as exemplified above is used widely as aphase-change recording material for an optical disc, and the material isbased on Sb₇₀Te₃₀ eutectic alloy and improvement such as the addition ofAg and In is performed thereto for improving an optical property and thelike.

Next, the result of the studies for a preferable composition range ofthe recording layer 52 will be described with using an example in thecase where the recording layer 52 is constituted of two chalcogenidelayers having different compositions as shown in FIG. 4. First, in orderto determine a composition range in which heat-resistance property ofthe first layer 52 a is high and its memory property is good, apreferable composition range is studied for the case where the recordinglayer has a single layer structure. FIG. 7 is an explanatory diagramshowing an example of a composition range of the recording layer in FIG.4. FIG. 8 is an explanatory diagram showing composition dependency of aratio of reset resistance/set resistance of the memory element in FIG.4. FIG. 9 is an explanatory diagram showing composition dependency of aset voltage of the memory element in FIG. 4. FIG. 10 is an explanatorydiagram showing composition dependency of the number of rewritable timesof the memory element in FIG. 4. FIG. 11 is an explanatory diagramshowing composition dependency of operation guaranteed temperature ofthe memory element in FIG. 4. FIG. 12 is an explanatory diagram showinganother example of composition range the recording layer in FIG. 4. Notethat composition dependencies of FIGS. 8 to 10 are those at roomtemperature.

A recording layer used in the studies is made of a phase-change material(chalcogenide material) containing, for example, at least either indium(In) or gallium (Ga), germanium (Ge), antimony (Sb) and tellurium (Te)with an appropriate composition ratio. When a memory element RMincluding such a recording layer is fabricated, composition dependenciesof each of the properties are as those shown below, and a hatched rangein FIG. 7 is obtained as a desirable composition.

The case where an In content is varied, that is, the compositiondependency in an x-axis direction of FIG. 7 will be described. As shownin FIG. 8, a ratio of reset resistance/set resistance is increased asthe amount of In increases. This is because the reset resistance(resistance value in amorphous state) is increased but an increasingeffect of the set resistance (resistance value in crystalline state) ishardly observed. More particularly, when an In composition is 7% ormore, the ratio of reset resistance/set resistance at room temperatureexceeds 500 to 1. When In is not contained, the resistance ratio isabout 100 to 1, but if In is added and the reset resistance at roomtemperature is increased 500 times or more, a resistance large ratio of100 to 1 or higher can be maintained even when a value of the resetresistance is remarkably decreased in the use environment at hightemperature of 130° C. or higher. In other words, high heat-resistanceproperty can be obtained. Note that an electric resistance value in ahigh-resistance state is 5 MΩ or more at room temperature and is 500 kΩor more at 130° C.

On the other hand, when the In composition is increased to 40%, as shownin FIG. 9, a set voltage required for a set operation is rapidlyincreased, which causes a problem in an actual operation. As describedabove, when the In concentration is 7 atomic % or lower, the resetresistance value is not increased, and also, since a data retentionproperty is insufficient, an effect of an operation reliability at hightemperature (heat-resistance property) cannot be obtained. On the otherhand, when the In concentration is 40 atomic % or higher, resistancereduction becomes difficult and time and current amount required for theset operation are increased, and therefore, is not suitable for use.

The case where Ge and Sb contents are varied, that is, compositiondependency in a y-axis direction of FIG. 7 will be described. When atotal amount of Ge and Sb is 10 atomic % or less, heat-resistanceproperty in a manufacturing process thereof is significantly decreasedto sublime a chalcogenide material in the manufacturing process, therebybeing impossible to continue the process. When Ge and Sb are small inamount, since In—Te bonding with strong ionicity is increased, Te tendsto be sublimated. However, when Ge and Sb are present appropriately,since Ge—Te and Sb—Te bondings with strong covalent bond are formed, itis expected that the sublimation of Te is suppressed.

On the other hand, if the total amount of Ge and Sb is larger than 40atomic %, there occur problems that the number of rewritable times isdecreased and the amount of current required for a reset operation isincreased. In particular, the number of rewritable times is decreasedwhen the content of Ge is large, and the amount of current required fora reset operation is increased when the content of Sb is large. Further,if the total amount exceeds 40 atomic % even when the content of Ge andthe content of Sb are approximately the same, the ratio of the resetresistance to the set resistance is disadvantageously decreased.

The case where a Te content is varied, that is, composition dependencyin a z-axis direction of FIG. 7 will be described. The results showingin FIGS. 10 and 11 are those in the case where the Ge and Sb contentsare adjusted to be equal to each other. As shown in FIG. 10, when Te is40 atomic % or less, the reset operation is disabled by rewriting onehundred thousand times or less. On the other hand, as shown in FIG. 11,when Te is 65 atomic % or more, an operation guaranteed temperaturethereof is lower than 130° C. and a requirement is not satisfied. Asdescribed above, when the Te content is small, phase-separation proceedstogether with the rewriting, thereby being unable to perform the resetoperation, and when it is too much, stability in a high-resistance statebecomes insufficient, and a sufficient data retention property cannot beobtained.

Therefore, according to the detailed studies for the compositiondependencies of the operation guaranteed temperature and the rewritingproperty described above, the conclusion that the hatched range shown inFIG. 7 is desired has been obtained. More specifically, a desirablecomposition range of the first layer 52 a in the chalcogenide layer(recording layer 52) is that at least either indium or gallium is 7atomic % or more and 40 atomic % or less, germanium is 5 atomic % ormore and 35 atomic % or less, antimony is 5 atomic % or more and 25atomic % or less, and tellurium is 40 atomic % or more and 65 atomic %or less. In this manner, in the first embodiment, it is possible torealize a memory element using a chalcogenide material having anexcellent data retention property and a proper resistance value even inthe use environment and manufacturing process at high temperature.

Also, a total amount obtained by summing the concentration of twoelements of Ge and Sb is shown in FIG. 7. However, since both theelements provide different actions, these amounts can be adjusted sothat both the elements can be contained within appropriate ranges. Forexample, in the case where a total amount of the Ge and Sb compositionsis constant in the entire constituent elements, when a ratio of Ge ishigh, volume change due to the phase change is large, and peeling occursat an interface between an electrode and a phase-change region byrewriting many times, and therefore, there occurs a problem that thenumber of rewritable times is limited. On the other hand, when a ratioof Sb is high, there occur problems that a current required for therewriting is increased, the reset resistance is lowered, and the dataretention property is decreased due to the instable amorphous state.FIG. 12 shows a more desirable composition range obtained in light ofthese points.

FIG. 12 shows an optimum composition in the case where the compositionsof each vertex are set to GeTe, Sb₂Te₃, and In₂Te₃. As a matter ofcourse, a part of each element can be replaced with an element of thesame group element in the periodic table. For example, a part of In canbe replaced with Ga or a part of Te can be replaced with Se. Acomposition range of FIG. 12 shows a preferable range in a compositionof Ge, Sb, and In when a concentration of Te is about 50 to 60 atomic %.Since a framework of the NaCl structure is constituted of Te having alarge atomic radius, if a Te concentration is near this composition,precipitation and phase separation of other components are hard to occureven if rewriting is performed many times, and therefore, it can beexpected that high reliability can be obtained.

In the composition range shown in FIG. 12, when GeTe concentration isincreased, a peeling occurs at an interface between a chalcogenidematerial and an electrode by rewriting many times, and the number ofrewritable times is limited to one hundred thousand times, and thus thisconcentration is inappropriate. When Sb₂Te₃ concentration is increased,there occur the problems that the reset-resistance is lowered, a currentamount required for the reset operation is increased, and the dataretention property is decreased. Also, when Sb₂Te₃ concentration islowered, there occurs a problem that a current amount required for theset operation is increased. Further, When In₂Te₃ concentration islowered, the resistance ratio is decreased to 500 to 1 or less, and whenit is increased, time and current amount required for the set operationare increased. By taking into consideration these points, the hatchedregion shown in FIG. 12 is obtained as a desirable range. A lowest andrightmost point of the composition range in FIG. 12 represents acomposition in which the In content is lowest, and the content thereofis about 10.5 atomic %.

Note that, in the description above, the result of studies in the caseof using the recording layer of the single layer structure has beenshown. However, the result of studies can be applied also to the case ofa two layer structure as shown in FIG. 4. More specifically, it isconfirmed that the composition range determined in the single layerstructure described above is optimum in the first layer 52 a in therecording layer 52 of FIG. 4. Also, the In concentration in therecording layer is changed in the film thickness direction, the firstlayer 52 a on the lower electrode TP side of FIG. 4 is adapted to havethe optimum composition in the description above, and the Inconcentration of the second layer 52 b thereon is set to be lower thanthat of the first layer 52 a by 5 atomic % or more, whereby aheat-resistance property at 260° C. for 3 minutes can be obtained. Atthis time, the heat-resistance property described above can be obtainedwhen the first layer 52 a has a film thickness in the range of 10 nm ormore and 40 nm or less. When the film thickness of the first layer 52 ais much thinner than the range described above, since a crystallizedregion reaches the most part in a chalcogenide layer including thesecond layer 52 b, there is a possibility that the heat-resistanceproperty becomes insufficient, and when it is much thicker, a currentreadily flows in the film surface direction like in the case where nosecond layer 52 b is provided, which becomes a cause of a failure suchas a property variation between elements. When a boundary between thefirst layer and the second layer is clear, a preferable result can beobtained if a film thickness ratio between the first layer and thesecond layer is 1 to 0.5 or more and 5 or less. When the film thicknessratio of the second layer is smaller than this, an effect obtained bythe two layer structure is not remarkable. Also, when the film thicknessratio of the second layer is larger than this, an excessive current isapplied to the first layer when the second layer is crystallized, and abreakage thereof occurs in many cases.

A preferable range of a whole film thickness including the first layer52 a and the second layer 52 b is 30 nm or more and 150 nm or less. Itdoes not matter if the boundary between the first layer 52 a and thesecond layer 52 b is clear or not (that is, a composition thereof may begradually changed). It is preferable that the average content of a groupII or group III element in the upper second layer 52 b in the filmthickness direction is set to 0 to 15 atomic %, and the difference ofthe both average contents is set to 5 atomic % or more. When the Incontent in the second layer 52 b is larger than 15 atomic % or thedifference in the contents is smaller than that described above, variouseffects obtained by the two layer structure as described in FIG. 4cannot be remarkably obtained.

Also, from a viewpoint of an average composition in the whole recordinglayer 52 of FIG. 4, since the second layer 52 b with Ge—Sb—Tecomposition in which the In concentration is low or In is not containedis provided, the In content is lowered compared with the optimumcomposition range of the first layer 52 a described above, andtherefore, it can be said that the following range is particularlypreferable. More specifically, in the average composition, In is in arange of 3 atomic % or more and 20 atomic % or less, Ge is in a range of10 atomic % or more and 25 atomic % or less, Sb is in a range of 10atomic % or more and 25 atomic % or less, and Te is in a range of 45atomic % or more and 65 atomic % or less. Further, a more preferablerange of the In average content is 7 atomic % or more and 15 atomic % orless. These ranges are almost the same even when In is replaced by Ga.However, the difficulty when Ga is used is that Ge is liquefied due toits low melting point when it is liberated in a film forming apparatus.

Also, according to another study result, by providing a high meltingpoint material layer with a thickness of 1 nm or more and 5 nm or lessat the interface between the first layer 52 a and the second layer 52 bto prevent an interdiffusion between the layers, a gentle decrease of aheat-resistance property caused by rewriting many times can beprevented. As the high melting point material layer, for example, anoxide such as tantalum pentoxide, a nitride such as tantalum nitride orsilicon nitride, a carbonized material such as silicon carbide andothers can be applied.

In the present embodiment, the chalcogenide material containing at leasteither Ga or In, Ge, Sb, and Te is shown. However, it is possible toreplace a part of these elements by other elements. For example, a partof Te may be replaced by Se (selenium). Se has such effects that a dataretention property is improved, it withstands for a longer period in asoldering process, and it can prevent oxidation in a manufacturingprocess. On the other hand, when the Se content exceeds one fifth of Te,the time required for the set operation becomes longer to 5 μs or more.Therefore, it is necessary to select and use the appropriate content inaccordance with the usage within a range where such problems do notoccur.

Also, for the purpose of speed-up of the set operation, at least oneelement of either Sn of Pb may be contained to replace a part or all ofGe, and Bi may be contained to replace a part or all of Sb. Since theseelements can achieve the speed-up of the set operation while maintaininga solder-reflow resistance in a reset state, they do not hinder theeffects described above. However, a retention lifetime in the resetstate is slightly shortened. In addition, H, B, C, O, Si, P, S, As, Au,Ag, Cu, Ti, Zr, Hf, V, Nb, Ta, Cr, Mn, Fe, Co, Ni, Rh, and Pd of 10atomic % or less may be contained. An improvement in the number ofrewritable times can be expected by the addition of these elements.

Next, a manufacturing process of a semiconductor device of FIG. 3 willbe described with reference to the drawings. FIGS. 13 to 23 are crosssectional views showing the main portions in a manufacturing process ofa semiconductor device according to the first embodiment. First, MIStransistors as shown in FIG. 13 are formed by using a well-knownmanufacturing process. In FIG. 13, on a main surface of a semiconductorsubstrate (semiconductor wafer) 11 made of, for example, a p-type singlecrystal silicon, element isolation regions 12 made of an insulator areformed by STI (Shallow Trench Isolation) method, LOCOS (LocalOxidization of Silicon) method or the like. By the formation of theelement isolation regions 12, active regions whose periphery is definedby the isolation regions 12 are formed on the main surface of thesemiconductor substrate 11.

On the main surface of the semiconductor substrate 11, p-type wells 13 aand 13 b and a n-type well 14 are formed. Of these, the p-type well 13 ais formed in the memory cell region MARE, and the p-type well 13 b andthe n-type well 14 are formed in the logic circuit region. Also, forexample, by using thermal oxidation method and the like, an insulator 15for a gate insulator made of a thin silicon oxide film or a siliconnitride film is formed on front surfaces of the p-type wells 13 a and 13b and the n-type well 14. A film thickness of the insulator 15 can be,for example, about 5 to 10 nm. On the insulator 15, gate electrodes 16a, 16 b and 16 c made of a polycrystalline silicon film with lowresistance are formed. Note that, by doping impurities in the filmformation or after the film formation, the gate electrodes 16 a and 16 bbecome polysilicon films doped with a n-type impurity, and the gateelectrode 16 c becomes a polysilicon film doped with a p-type impurity.

Also, by the ion implantation of an n-type impurity or the like, then⁻-type semiconductor regions 17 a are formed in the regions on bothsides of the gate electrode 16 a of the p-type well 13 a, and then⁻-type semiconductor regions 17 b are formed in the regions on bothsides of the gate electrode 16 b of the p-type well 13 b. Also, by theion implantation of a p-type impurity or the like, the p⁻-typesemiconductor regions 17 c are formed in the regions on both sides ofthe gate electrode 16 c of the n-type well 14. On the sidewalls of thegate electrodes 16 a, 16 b and 16 c, the sidewalls 18 a, 18 b and 18 care formed by, for example, depositing an insulator made of a siliconoxide film, a silicon nitride film, or a stacked film thereof on thesemiconductor substrate 11 and then performing anisotropic etching tothis insulator.

Further, by the ion implantation of a n-type impurity or the like, then⁺-type semiconductor regions 19 a are formed in the regions on bothsides of the gate electrode 16 a and the sidewalls 18 a of the p-typewell 13 a, and the n⁺-type semiconductor regions 19 b are formed in theregions on both sides of the gate electrode 16 b and the sidewalls 18 bof the p-type well 13 b. Further, by the ion implantation of a p-typeimpurity or the like, the p⁺-type semiconductor regions 19 c are formedin the regions on both sides of the gate electrode 16 c and thesidewalls 18 c of the n-type well 14. Then, front surfaces of the gateelectrodes 16 a, 16 b and 16 c, the n⁺-type semiconductor regions 19 aand 19 b, and the p⁺-type semiconductor region 19 c are exposed and ametal film such as a cobalt (Co) film is deposited and thermal processis performed thereto, whereby metal silicide layers 25 are formed oneach of the front surfaces thereof. In this manner, a structure of FIG.13 is obtained.

Next, as shown in FIG. 14, the insulator (interlayer insulating film) 31is formed on the semiconductor substrate 11 so as to cover the gateelectrodes 16 a, 16 b and 16 c. The insulator 31 is made of, forexample, a silicon oxide film or the like. The insulator 31 can beformed from a stacked layer of a plurality of insulators. After formingthe insulator 31, CMP process or the like is performed according to needto planarize an upper surface of the insulator 31. Next, dry etching isperformed to the insulator 31 with using a photoresist pattern (notshown) formed on the insulator 31 by a photolithography method as anetching mask, thereby forming contact holes in the insulator 31. At thebottom portion of the contact holes, a part of the main surface of theinsulator 31, for example, a part of the semiconductor regions DN1 toDN4, DNC, DP1 and DP2 (metal silicide layers 25 thereof), a part of thegate electrodes 16 a, 16 b and 16 c (metal silicide layers 25 thereof)or others are exposed.

Next, the plugs 33 are formed in the contact holes. At this time, forexample, the conductive barrier film 33 a is formed by sputtering or thelike on the insulator 31 including the inside of the contact holes, andthen the tungsten film 33 b is formed by CVD or the like on theconductive barrier film 33 a. Then, unnecessary portions of the tungstenfilm 33 b and the conductive barrier film 33 a on the insulator 31 areremoved by CMP, an etch-back technique, and the like. In this manner,the plugs 33 formed of the tungsten film 33 b and the conductive barrierfilm 33 a left and embedded in the contact holes can be formed.

Next, as shown in FIG. 15, the insulator 34 is formed on the insulator31 in which the plugs 33 are embedded. Then, with using a photoresistpattern (not shown) formed by using photolithography on the insulator 34as an etching mask, dry etching is performed to the insulator 34,thereby forming wiring trenches in the insulator 34. At the bottomportion of the wiring trenches 35, the upper surfaces of the plugs 33are exposed. Note that, of the wiring trenches, the wiring trencheswhich expose the plugs 33 formed on the drain regions (semiconductorregions DN3 and DN4) of the QM1 and QM2 in the memory cell region MAREcan be formed as hole-shaped (connection-hole-shaped) patterns havingplanar dimensions larger than those of the plugs 33 exposed therefrominstead of trench-shaped patterns.

Next, the wirings M1 are formed in the wiring trenches. At this time,for example, after the conductive barrier film 36 a is formed on theinsulator 34 including the inside (bottom portion and sidewalls) of thewiring trenches by sputtering or the like, the main conductor film 36 bmade of a tungsten film or the like is formed thereon by CVD or thelike, and then, unnecessary portions of the main conducive film 36 b andthe conductive barrier film 36 a on the insulator 34 are removed by CMP,an etch-back technique, and the like. In this manner, the wirings M1formed of the main conductor film 36 b and the conductive barrier film36 a left and embedded in the wiring trenches 35 can be formed. Notethat the wiring M1 is not limited to the above-described embeddedtungsten wiring, and various modifications and alterations can be made.For example, a tungsten wiring other than the embedded tungsten wiringor an aluminum wiring can be used.

Next, as shown in FIG. 16, on the insulator 34 in which the wirings M1are embedded, an insulator (interlayer insulating film) 41 is formed.Subsequently, with using a photoresist pattern (not shown) formed byusing photolithography on the insulator 41 as an etching mask, dryetching is performed to the insulator 41, thereby forming through holes(opening portion, connection hole) in the insulator 41. The throughholes are formed in the memory cell region MARE, and at the bottomportion of the through holes, an upper surface of the wiring M1corresponding to the semiconductor regions DN3 and DN4 of the QM1 andQM2 is exposed.

Next, the plugs 43 are formed in the through holes. At this time, forexample, after the conductive barrier film 43 a is formed on theinsulator 41 including the inside of the through holes by sputtering orthe like, the tungsten film 43 a is formed thereon by CVD or the like,and then, unnecessary portions of the tungsten film 43 b and theconductive barrier film 43 a on the insulator 41 are removed by CMP, anetch-back technique, and the like. In this manner, the plugs 43 formedof the tungsten film 43 b and the conductive barrier film 43 a left andembedded in the contact holes can be formed. As described above, theplugs 43 are formed by filling the opening portions (through hole)formed in the insulator 41 with a conductor material.

Note that, in the present embodiment, the plugs 43 are formed by fillingthe through holes with the tungsten film 43 b. However, a metal filmcapable of improving the planarity of an upper surface of the plug 43after the CMP process (metal with good CMP planarity) can be usedinstead of the tungsten film 43 b. For example, as the metal with goodCMP planarity, a molybdenum (Mo) film whose crystal grain size is smallcan be used instead of the tungsten film 43 b. The metal with good CMPplanarity has an effect to prevent a local phase-change in the recordinglayer 52 due to electric field concentration caused by an unevenness ofthe upper surface of the plug 43. As a result, uniformity of electricproperty, reliability of the number of rewritable times, andhigh-temperature-operation resistance property of a memory cell elementcan be further improved.

Next, as shown in FIG. 17, on the insulator 41 in which the plugs 43 areembedded, the peeling-preventing film 51, the recording layer 52, andthe upper electrode film 53 are formed (deposited) in order. A filmthickness (deposition thickness) of the peeling-preventing film 51 is,for example, about 0.5 to 5 nm, a film thickness (deposition thickness)of the recording layer 52 is, for example, about 50 to 150 nm, and afilm thickness (deposition thickness) of the upper electrode film 53 is,for example, about 50 to 200 nm.

Here, when the recording layer 52 is formed, for example, the sputteringmethod using inert gas such as Ar, Xe and Kr and two kinds of targets isapplied. First, for example, an In₃₀Ge₁₀Sb₁₀Te₅₀ layer with a filmthickness of about 10 to 40 nm is formed as a first layer, and aGe₂Sb₂Te₅ layer with a film thickness of about 40 to 110 nm is formedthereon as a second layer. Note that, instead of the Ge₂Sb₂Te₅ layer, alayer with an In concentration lower than that of the In₃₀Ge₁₀Sb₁₀Te₅₀layer, for example, an In₁₀Ge₁₅Sb₂₀Te₅₅ layer can be formed for thesecond layer. In this case, there is a possibility that crystallizationin an upper portion becomes difficult to some extent. However, an effectsimilar to the case of using the Ge₂Sb₂Te₅ layer can be obtained. Also,in the case of using sputtering equipment capable of sputtering twotargets at the same time, a composition may be smoothly varied at aboundary portion of two layers.

Next, as shown in FIG. 18, by using a photolithography method and a dryetching method, the stacked film including the peeling-preventing film51, the recording layer 52 and the upper electrode film 53 is patterned.By this means, the memory elements RM including the stacked pattern ofthe upper electrode film 53, the recording layer 52 and thepeeling-preventing film 51 are formed on the insulator 41 in which theplugs 43 are embedded. The peeling-preventing film 51 can be also usedas an etching-stopper film when the upper electrode film 53 and therecording layer 52 are dry-etched.

Next, as shown in FIG. 19, the insulator (etching stopper film) 61 isformed on the insulator 41 so as to cover the memory elements RM. Inthis manner, the insulator 61 is formed on an upper surface of the upperelectrode film 53, a sidewall (side surface) of the recording layer 52and the insulator 41 other than those. A material film that can beformed at the temperature at which the recording layer 52 does notsublimate (for example 400° C. or lower) is preferably used as theinsulator 61. For example, when a silicon nitride film is used as theinsulator 61, the silicon nitride film can be preferably formed at thetemperature at which the recording layer 52 does not sublimate (forexample 400° C. or lower) by using the plasma CVD or the like, wherebythe sublimation of the recording layer 52 at the time of the formationof the insulator 61 can be prevented.

Next, as shown in FIG. 20, the insulator (interlayer insulating film) 62is formed on the insulator 61 as an interlayer insulating film.Therefore, the insulator 62 is formed on the insulator 61 so as to coverthe stacked pattern (memory element 54) of the upper electrode film 53,the recording layer 52, and the peeling-preventing film 51. Afterforming the insulator 62, an upper surface of the insulator 62 can beplanarized by performing the CMP process and the like according to need.Thereafter, a photoresist pattern is formed on the insulator 62 by usinga photolithography method. Then, the insulator 62 is dry-etched withusing the photoresist pattern as an etching mask, thereby formingthrough holes (opening portion, connection hole) 65 a in the insulator62.

In the dry etching to the insulator 62, the dry etching is performedunder the condition that the insulator 62 (silicon oxide) is easier tobe etched than the insulator 61 (silicon nitride) (that is, conditionthat an etching speed (etching rate) of the insulator 62 is higher thanthat of the insulator 61) so as to make the insulator 61 function as theetching stopper film. In this dry etching, for example, an etchingmethod with a selectivity of 10 or more, in which the insulator 62 madeof silicon oxide is etched but the insulator 61 serving as the etchingstopper is not etched, is used. At this stage, the insulator 61 isexposed at the bottom portion of the through hole 65 a. However, sincethe insulator 61 functions as the etching stopper, the etching stops inthe state where the insulator 61 is exposed at the bottom portion of thethrough hole 63, and the upper electrode film 53 of the memory element54 is not exposed.

Then, as shown in FIG. 21, a dry etching is performed under thecondition that the insulator 61 (silicon nitride) is easier to bedry-etched than the insulator 62 (silicon oxide) (that is, conditionthat an etching speed of the insulator 61 is higher than that of theinsulator 62), and the insulator 61 exposed at the bottom portion of thethrough hole 65 a is dry-etched and removed. By this means, at thebottom portion of the through hole 65 a, at least a part of the upperelectrode 53 of the memory element RM is exposed. This dry etching ispreferably performed by anisotropic dry etching. Thereafter, thephotoresist pattern is removed.

Next, as shown in FIG. 22, the insulators 62, 61 and 41 are dry-etchedwith using a photoresist pattern (not shown) formed on the insulator 62by using a photolithography method as an etching mask, thereby forming athrough hole (opening portion, connection hole) and exposing an uppersurface of the wiring M1 formed in the logic circuit region LARE.Thereafter, the photoresist pattern is removed. Next, the plugs 64 and66 are formed in the through hole of the LARE and the through holes 65 adescribed above. At this time, for example, after forming the conductivebarrier film 67 a on the insulator 62 including the inside of thethrough holes by the sputtering method and the like, the tungsten film67 b is formed thereon by the CVD method and the like, and then, theunnecessary portions of the tungsten film 67 b and the conductivebarrier film 67 a on the insulator 62 are removed by the CMP, anetch-back technique or the like. In this manner, the plugs 64 and 66embedded in each of the through holes can be formed. Note that analuminum (Al) film, an aluminum alloy film (main conductor film) or thelike can be also used instead of the tungsten film 67 b.

Next, as shown in FIG. 23, the wirings M2 are formed as a second layerwiring on the insulator 62 in which the plugs 64 and 66 are embedded.For example, on the insulator 62 in which the plugs 64 and 66 areembedded, the conductive barrier film 71 a and the aluminum (Al) film oraluminum alloy film 71 b are formed in order by sputtering method or thelike, and then patterned by using photolithography method and dryetching method, thereby forming the wirings M2. The wiring M2 is notlimited to the above-described aluminum wiring, and variousmodifications and alterations can be made. For example, a tungstenwiring or a copper wiring (implanted copper wiring) can be used instead.

Thereafter, an insulator (not shown) serving as an interlayer insulatingfilm is formed on the insulator 62 so as to cover the wirings M2, andupper wiring layers (wirings of third and subsequent layers) and othersare formed thereon. However, the illustration and description thereofare omitted here. Then, after performing the hydrogen annealing at about400° C. to 450° C., a semiconductor device (semiconductor memory device)is completed.

By the way, as a method for ensuring the heat-resistance propertydifferent from the first embodiment, there is a method in which a filmthickness of a chalcogenide layer is reduced so as to suppress theoccurrence of a problem of resistance increase even when hightemperature in the reset state is maintained. It is believed that, whenthis method is used, a current readily flows in a film thicknessdirection, and an influence of atomic arrangement change except for anormal crystallization at an upper portion of an outer edge of a plug ishard to appear. However, in the case of film thickness reduction, thereis a tendency that a yield of an operable element decreases more as thethickness becomes thinner. In the case of the first embodiment, since anupper portion of the chalcogenide layer (for example, the second layer52 b) is easily crystallized and the resistance thereof is decreased, aneffect similar to the case of film thickness reduction can be obtained,and the decrease in an operation yield does not occur because its filmthickness is large.

Also, in the above-described method in which a film thickness of achalcogenide layer is reduced, the reduction of a set voltage isexpected, but practically, the reduction is hardly achieved. On theother hand, in the case of the first embodiment, an additive-free GeSbTefilm serving as an example of the second layer 52 b is crystallizedearlier because of its low set voltage, and potential gradient isincreased by an accumulation of holes at an interface thereof, so thathighly efficient impact ionization which triggers the low-voltage setoperation is induced to the first layer 52 a containing a lot of In.Therefore, it is expected to achieve the low-voltage set.

Moreover, another manufacturing method is known, in which right afterforming the chalcogenide material layer or after forming a tungsten or atungsten alloy layer of 2 nm or more and 15 nm or less on a frontsurface of the chalcogenide layer, high-power laser optical beam ofabout 1 to 4 W is irradiated thereto while scanning the same with anoval shaped beam spot, thereby performing the crystallization. In thiscase, in the recording layer 52 of the first embodiment, an upperportion to which light is incident has a composition to crystallizeeasily, and a clear crystal of cubic lattice is formed to a lowerportion in accordance with the crystallization at an upper portion, andtherefore, the time required for an initial crystallization by a currentcan be reduced. Note that, after the laser irradiation, an upperelectrode layer equivalent to the film thickness of the rest is formed.

The typical effects obtained by using the semiconductor device of thefirst embodiment described above will be briefly described below. Asshown in FIG. 4, the recording layer 52 is formed of at least two layersor more, and a concentration of a group II or group III elementcontained in a layer on an lower electrode side of the recording layer52 is made higher than that in a layer on an upper electrode side,whereby a semiconductor device provided with a high heat-resistanceproperty and a stable data retention property can be realized.

Second Embodiment

The recording layer 52 in the memory element RM according to the firstembodiment described above is made of the phase-change materialcontaining at least either indium (In) or gallium (Ga), germanium (Ge),antimony (Sb), and tellurium (Te) with an appropriate composition ratio.In the second embodiment, the case where a constituent element of 10% orless of the recording layer 52 is replaced by nitrogen will bedescribed. Note that, except for that the constituent element of 10% orless is replaced by nitrogen, the second embodiment is the same as thefirst embodiment described above, and therefore, the description of anoverlapping part is omitted.

In the case where the constituent element of the chalcogenide material(phase-change material) containing at least either indium or gallium,germanium, antimony, and tellurium is replaced by nitrogen, suchadvantages as that data retention property at high temperature isimproved, characteristic variation is reduced because of fine crystalgrain, and others can be obtained.

The recording layer included in the semiconductor device of the secondembodiment is formed by, for example, a sputtering method using inertgases such as Ar, Xe and Kr as described in the first embodiment, but inthe formation of the recording layer in the second embodiment, nitrogengas is mixed into these inert gases. FIG. 24 shows activation energy forcrystallization when a film is formed by mixing nitrogen gas into Ar gasin the sputtering of the chalcogenide material. As shown in FIG. 24,when nitrogen is added, the activation energy for crystallization isdecreased. This is because the crystallization at high temperature issuppressed. Note that data retention property in an operationtemperature region is not deteriorated.

Therefore, in the recording layer, while maintaining the data retentionproperty in a normal operation temperature region, data retention lifeat a temperature higher than that is improved. Accordingly, for example,an effect to withstand the heat load in a packaging process in whichtemperature is increased higher than actual use environmentaltemperature is brought. However, since characteristic variation byrewriting is large if an amount of nitrogen is too much, it isappropriate to set it to 10% or less. Note that, although a nitrogencontent in the first layer of the recording layer may be the same asthat in the second layer, if making a difference therebetween, thecontent in the first layer is preferably set to 1.5 times or more and 5times or less the content in the second layer in terms of theheat-resistance property.

Third Embodiment

In a semiconductor device according to a third embodiment, thermalprocess is performed to the semiconductor devices according to the firstand second embodiments described above. Here, thermal process in apackaging process will be described with reference to FIGS. 25 and 26.FIG. 25 is an explanatory diagram showing a temperature profile insolder reflow process. FIG. 26 is an explanatory diagram showing dataretention property when preheat treatment for the solder reflow processis performed.

When packaging a semiconductor device such as a microcomputer providedwith the memory element RM, for example, solder reflow process isperformed. When lead-free solder is used, a temperature of solder reflowprocess is about 260° C. at a maximum, and the semiconductor deviceprovided with the memory element RM is exposed to a high-temperatureenvironment much beyond a normal operation environment.

However, as shown in FIG. 25, when a relatively high temperature ismaintained for a certain period in a range not over a crystallizationtemperature of a chalcogenide material (phase-change material), thehigh-resistance state is further stabilized. This is probably becausethe crystal nucleation site becomes inactive and the crystallization isdifficult to proceed, and this has a characteristic that the dataretention property is further improved.

FIG. 26 shows the decrease of the resistance in a reset state from aninitial value with respect to the two samples including one which istemporarily kept at 180° C. for 90 seconds and then heated to 260° C.and the other which is directly heated to 260° C. without being kept, inthe packaging process by the lead-free soldering reflow. According tothe results shown in FIG. 26, the resistance of the sample through thepreheat treatment is hard to be lowered. Therefore, the semiconductordevice that has been placed under an environment of a temperatureprofile in which the temperature is kept for a predetermined period oftime at a relatively low temperature considered to be lower than thecrystallization temperature of the recording layer and is then increasedto a peak temperature higher than the crystallization temperature isprovided with the memory elements RM suitable for the packaging process.

According to the third embodiment, a highly reliable semiconductordevice which can maintain a memory state even in a soldering reflowprocess and has a high resistance ratio and an excellent data retentionproperty even at high temperature can be achieved. Further, thesemiconductor device according to the third embodiment can also be usedeven under such a high-temperature environment as in a microcomputer forcontrolling an automobile engine.

Fourth Embodiment

FIG. 27 is a circuit diagram showing a configuration example in asemiconductor device according to a fourth embodiment of the presentinvention. The circuit configuration of the fourth embodiment is oneexample of a memory array configuration using the recording layer madeof the chalcogenide material described in the first and secondembodiments and the manufacturing process thereof, and it has acharacteristic that it is operated by applying a high voltage to anupper electrode side compared with a lower electrode. The semiconductordevice of FIG. 27 includes a memory array, a multiplexer MUX, a row(row) decoder XDEC, a column (column) decoder YDEC, a pre-charge circuitPC, a sense amplifier SA, and a rewriting circuit PRGM.

In the memory array, memory cells MC11 to MCmm are disposed at each ofthe intersections of word lines WL1 to WLm and bit lines BL1 to BLn.Each memory cell has a configuration in which a memory element RM and amemory cell transistor QM connected in series are interposed between thebit line BL and a ground voltage VSS terminal and one end of the memoryelement RM is connected to the bit line BL. Here, the memory element RMhas a configuration as described in FIG. 4 and others. Morespecifically, the upper electrode 53 of FIG. 4 is connected to the bitline BL, and the lower electrode TP of FIG. 4 is connected to one end ofthe memory cell transistor QM.

The word line WL serving as an output signal of the row decoder XDEC isconnected to a gate of the memory cell transistor QM. The pre-chargecircuit PC, the sense amplifier SA, and the rewriting circuit PRGM areconnected to a common data line CD. The pre-charge circuit PC isactivated by a pre-charge activation signal PCE of high level (here, apower supply voltage VDD) to drive the common data line CD to a readingvoltage VRD (voltage level thereof will be described later).

The multiplexer MUX includes a column selecting switch row CSWA and adischarging circuit DCCKT. The column selecting switch row CSWA iscomposed of a plurality of CMOS transfer gates (column selecting switch)CSW1 to CSWn each interposed between the bit lines BL1 to BLn and thecommon data line CD. Column select line pairs (YS1T and YS1B) to (YSnTand YSnB) serving as output signals of the column decoder YDEC areconnected to the gate electrodes of the CMOS transfer gates CSW1 toCSWn. By activating one of the column select line pairs (YS1T and YS1B)to (YSnT and YSnB), the corresponding CMOS transfer gate is activated,and one of the bit lines BL1 to BLn is connected to the common data lineCD.

The discharging circuit DCCKT is composed of NMOS transistors MN1 to MNneach interposed between the bit lines BL1 to BLn and the ground voltageVSS terminal. Column select lines YS1B to YSnB are connected to the gateelectrodes of the NMOS transistors MN1 to MNn, respectively. In astand-by state, the column select lines YS1B to YSnB are maintained atthe power supply voltage VDD, whereby the NMOS transistors MN1 to MNnare turned on, and the bit lines BL1 to BLn are driven to the groundvoltage VSS.

In the configuration described above, the reading operation as shown inFIG. 28 is performed. Hereinafter, description will be made on theassumption that the memory cell MC11 is selected. First, the columnselecting switch CSW1 corresponding to the column select line pair (YS1Tand YS1B) selected by the column decoder YDEC is turned on, so that thebit line BL1 and the common data line CD are connected. At this time, bythe activated pre-charge circuit PC, the bit line BL1 is pre-charged tothe reading voltage VRD through the common data line CD. This readingvoltage VRD is designed to a voltage level between the power supplyvoltage VDD and the ground voltage VSS so as not to cause a damage tostored information.

Next, the pre-charge activation signal PCE of the power supply voltageVDD is driven to the ground voltage VSS to put the pre-charge circuit PCinto an inactive state. Further, a memory cell transistor QM on the wordline (WL1) selected by the row decoder XDEC is turned on, so that acurrent path is formed in the memory cell MC11 and a read signal isgenerated to the bit line BL1 and the common data line CD.

Since a resistance value in the selecting memory cell differs dependingon the stored information, the voltage outputted to the common data lineCD differs depending on the stored information. In this case, in thecase where the stored information is ‘1’, the resistance value in thememory cell is low, so that the bit line BL1 and the common data line CDare discharged toward the ground voltage VSS to be a voltage lower thana reference voltage VREF. On the other hand, in the case where thestored information is ‘0’, the resistance value in the memory cell ishigh, so that the bit line BL1 and the common data line CD are held in apre-charge state, that is, at the reading voltage VRD. By specifyingthis difference by the sense amplifier SA, the stored information of theselecting memory cell is read. Lastly, the column select line (YS1T andYS1B) is put into an inactive state to turn on the transistor MN1, sothat the bit line BL1 is driven to the ground voltage VSS, and at thesame time, the pre-charge activation signal PCE of the ground voltageVSS is driven to the power supply voltage VDD to activate the pre-chargecircuit PC, thereby returning to the stand-by state.

FIG. 29 shows a writing operation of the memory array shown in FIG. 27.Also in this case, similar to FIG. 28, description will be made on theassumption that the memory cell MC11 is selected. Firstly, thepre-charge activation signal PCE of the power supply voltage VDD isdriven to the ground voltage VSS to put the pre-charge circuit into aninactive state. Then, the column selecting switch CSW1 corresponding tothe column select line pair (YS1T and YS1B) selected by the columndecoder YDEC is turned on, so that the bit line BL1 and the writingcircuit PRGM are connected through the common data line CD. Next, thememory cell transistor QM on the word line (WL1) selected by the rowdecoder XDEC is turned on, so that a current path is formed in thememory cell MC11 and the writing current flows in the bit line BL1.

The writing circuit PRGM is designed so that the writing current and anapplication time thereof take the values corresponding to the storedinformation. In this case, a large reset current IR is applied for ashort period when the stored information is ‘0’. On the other hand, whenthe stored information is ‘1’, a set current IS smaller than the resetcurrent IR is applied for a longer period than that of the resetcurrent. Lastly, the column select line pair (YS1T and YS1B) is put intoan inactive state to turn on the transistor MN1, so that the bit lineBL1 is driven to the ground voltage VSS, and at the same time, thepre-charge activation signal PCE of the ground voltage VSS is driven tothe power supply voltage VDD to activate the pre-charge circuit PC,thereby returning to the stand-by state.

In the foregoing, in the fourth embodiment, the semiconductor device asshown in FIG. 27 is formed by using the memory element RM described inthe first and second embodiments, so that a semiconductor deviceprovided with a high heat-resistance property and a stable dataretention property can be realized. Also, like in the configuration andthe operation described above, rewriting for the memory element RM ispreferably performed by applying an electric field from the upperelectrode 53 toward the lower electrode TP. The reason thereof is thatpositive ions (for example, In ion) can be kept in a lower layer (firstlayer 52 a). Accordingly, since a composition distribution in a filmthickness direction in the recording layer 52 is stably maintained, thenumber of rewritable times can be improved, and a more stable dataretention property can be realized.

Fifth Embodiment

In a fifth embodiment, one example of a circuit configuration and anoperation thereof different from the fourth embodiment described abovewill be described. FIG. 30 is a circuit diagram showing a configurationexample in the semiconductor device according to the fifth embodiment ofthe present invention. In the semiconductor device shown in FIG. 30,similar to FIG. 27 described above, a memory array configuration havinga memory cell of n×m bits is shown. Similarly, the elements constitutingthe memory cell are also the memory cell transistor QM and the memoryelement RM by the variable resistance using a chalcogenide material. Thefifth embodiment has a characteristic that one more bit line is added tothe one bit line in FIG. 27 and memory cells are disposed at theintersections of the bit line pairs and word lines, so that a voltage ina reverse direction can be applied to the memory element. Hereinafter,as focusing on a different point from the FIG. 27, a configuration of asemiconductor device shown in FIG. 30 will be described.

The semiconductor device shown in FIG. 30 includes a common dischargecircuit CDCCKT in addition to a memory array, a multiplexer MUX, a row(row) decoder XDEC, a column (column) decoder YDEC, a reading circuitRC, and a rewriting circuit PRGM. The memory array has a configurationin which memory cells MC11 to MCmn are disposed at the intersections ofthe word lines WL1 to WLm and the bit line pairs (BL1L and BL1R) to(BLnL and BLnR). Each memory cell has a configuration in which a memoryelement RM and a selecting transistor QM connected in series areinterposed between the bit lines BL1L to BLnL and the bit lines BL1R toBLnR. In this case, the memory element RM has a configuration describedin FIG. 4 and others, in which the upper electrode 53 of FIG. 4 isconnected to bit lines BL1L to BLnL sides and the lower electrode TP ofFIG. 4 is connected to one end of the memory cell transistor QM.

The reading circuit RC, the rewriting circuit PRGM, and the commondischarging circuit CDCCKT are connected to the common data line pair(CDL and CDR). Portions corresponding to the bit lines BL1R to BLnR areadded to a column selecting switch row CSWA and a discharging circuitDCCKT in the multiplexer MUX. More specifically, CMOS transfer gates(column selecting switch) CSW1R to CSWnR interposed between the bitlines BL1R to BLnR and the common data line CDR are added to the columnselecting switch row CSWA. Column select line pairs (YS1T and YS1B) to(YSnT and YSnB) serving as output signals of the column decoder YDEC areconnected to the gate electrodes of the CMOS transfer gates CSW1 to CSWnand CSW1R to CSWnR, respectively. By activating one of the column selectline pairs (YS1T and YS1B) to (YSnT and YSnB), a corresponding pair ofthe CMOS transfer gates is activated, and one pair of the bit line pairs(BL1L and BL1R) to (BLnL and BLnR) is connected to the common data linepair (CDL and CDR).

NMOS transistors MN1R to MNnR interposed between the bit lines BL1R toBLnR and the ground voltage VSS are added to the discharging circuitDCCKT. Column select lines YS1B to YSnB are connected to the gateelectrodes of the NMOS transistors MN1R to MNnR, respectively. In astand-by state, the column select lines YS1B to YSnB are maintained atthe power supply voltage VDD, whereby the NMOS transistors MN1L to MNnLand MN1R to MNnR are turned on, and the bit line pairs (BL1L and BL1R)to (BLnL and BLnR) are driven to the ground voltage VSS.

FIG. 31 is a circuit diagram showing a detailed configuration example ofthe common discharging circuit CDCCKT, the reading circuit RC, and therewriting circuit PRGM of FIG. 30. The discharging circuit DCCKTincludes NMOS transistors MN101 and MN102 and a NOR circuit NR101. TheMN101 is interposed between the common data line CDL and the groundvoltage VSS, and the MN102 is interposed between the common data lineCDR and the ground voltage VSS. Also, an output terminal of the NORcircuit NR101 is connected to each of gate electrodes of the NMOStransistors MN101 and MN102.

A reading activation signal RD and a rewriting activation signal WTdescribed later are inputted to input terminals of the NOR circuitNR101, respectively. Since these signals are maintained at the groundvoltage VSS in a stand-by state, when the transistors MN101 and MN102are turned on, the common data line pair (CDL and CDR) is driven to theground voltage VSS. On the other hand, since the reading activationsignal RD is driven to the power supply voltage VDD in a readingoperation and the rewriting activation signal WT is driven to the powersupply voltage VDD in a rewriting operation, the transistors MN101 andMN102 are cut off in these operations.

The reading circuit RC is constituted of NMOS transistors MN111 andMN112, the pre-charge circuit PC, and the sense amplifier SA. Thepre-charge circuit PC is connected to the sense amplifier SA by a nodeSND. The pre-charge circuit PC is activated by a pre-charge activationsignal PCE of high level (here, the power supply voltage VDD) to drivethe node SND and others to the reading voltage VRD. The transistor MN111is interposed between the common data line CDL and the sense amplifierSA, and the transistor MN112 is interposed between the common data lineCDR and the ground voltage VSS, respectively. The reading activationsignal RD is inputted to the gate electrodes of these transistors.

Since the reading activation signal RD is maintained at the groundvoltage VSS in a stand-by state as described above, in this case, thetransistors MN111 and MN112 are cut off. On the other hand, since thereading activation signal RD which is at the ground voltage VSS isdriven to the power supply voltage VDD in a reading operation, thetransistors MN111 and MN112 are turned on, whereby the common data lineCDL is connected to the pre-charge circuit PC and the sense amplifierSA, and the common data line CDR is connected to the ground voltage VSS.In the configuration described above, a source electrode of thetransistor QM in a selected memory cell is driven to the ground voltageVSS from the common data line CDR through the bit lines BL1R to BLnR inthe reading operation. Also, a reading signal corresponding to thestored information is inputted to the sense amplifier SA from the bitlines BL1L to BLnL through the common data line CDL, thereby being ableto perform the reading operation similar to that of FIG. 28.

The rewriting circuit PRGM is constituted of common data line drivercircuits CDDL and CDDR, COMS transfer gates CSW151 and CSW152, a NANDcircuit ND151, and an inverter circuit IV151. The CSW151 is interposedbetween the common data line CDL and the common data line driver circuitCDDL, and the CSW152 is interposed between the common data line CDR andthe common data line driver circuit CDDR. The rewriting activationsignals WT and WTB obtained by performing an AND operation of a setactivation signal SETB and a reset activation signal RSTB by using theNAND circuit ND151 and the inverter circuit IV151 are respectivelyconnected to these gate electrodes.

Here, since the set activation signal SETB and the reset activationsignal RSTB are maintained at the power supply voltage VDD in a stand-bystate, the rewriting activation signal WT is maintained at the groundvoltage VSS and the rewriting activation signal WTB is maintained at thepower supply voltage VDD, whereby the common data lines CDL and CDR andthe common data line driver circuits CDDL and CDDR are cut off. On theother hand, since the set activation signal SETB or the reset activationsignal RSTB is driven to the ground voltage VSS in a rewritingoperation, the WT is driven to the power supply voltage VDD and the WTBis driven to the ground voltage VSS to turn on the CSW151 and CSW152,respectively, whereby the common data lines CDL and CDR and the commondata line driver circuits CDDL and CDDR are connected to each other.

The common data line driver circuit CDDL is constituted of a PMOStransistor MP131, NMOS transistors MN131 and MN132, and an invertercircuit IV131. The transistor MP131 and the NMOS transistor MN131 areinterposed between the set voltage VS and the ground voltage VSS, and adrain electrode thereof is a node N1. The node N1 and the transfer gateCSW151 are connected, and at the same time, the transistor MN132 isinterposed between the node N1 and the ground voltage VSS.

The set activation signal SETB is connected to a gate electrode of thetransistor MP131. When the set activation signal SETB which is at thepower supply voltage VDD is driven to the ground voltage VSS in the setoperation, the transistor MP131 is turned on, whereby the set voltage VSis applied to the common data line CDL through the transfer gate CSW151.A signal obtained by inverting the reset activation signal RSTB at theinverter circuit IV131 is connected to a gate electrode of thetransistor MN131. When the reset activation signal RSTB which is at thepower supply voltage VDD is driven to the ground voltage VSS in thereset operation, the transistor MN131 is turned on, whereby the groundvoltage VSS is applied to the common data line CDL through the transfergate CSW151. The rewriting activation signal WTB is connected to a gateelectrode of the transistor MN132. Since the rewriting activation signalWTB is maintained at the power supply voltage VDD in a stand-by state,the transistors MN132 is turned on, whereby the ground voltage VSS isapplied to the node N1.

The common data line driver circuit CDDR is constituted of a PMOStransistor MP141, NMOS transistors MN141 and MN142, and an invertercircuit IV141. The transistor MP141 and the NMOS transistor MN141 areinterposed between the reset voltage VR and the ground voltage VSS, anda drain electrode thereof is a node N2. The node N2 and the transfergate CSW152 are connected, and at the same time, the transistor MN142 isinterposed between the node N2 and the ground voltage VSS.

The reset activation signal RSTB is connected to a gate electrode of thetransistor MP141. When the reset activation signal RSTB which is at thepower supply voltage VDD is driven to the ground voltage VSS in thereset operation, the transistor MP141 is turned on, whereby the resetvoltage VR is applied to the common data line CDR through the transfergate CSW152. A signal obtained by inverting the set activation signalSETB at the inverter circuit IV141 is connected to a gate electrode ofthe transistor MN141. When the set activation signal SETB which is atthe power supply voltage VDD is driven to the ground voltage VSS in theset operation, the transistor MN141 is turned on, whereby the groundvoltage VSS is applied to the common data line CDR through the transfergate CSW152. The rewriting activation signal WTB is connected to a gateelectrode of the transistor MN142. Since the rewriting activation signalWTB is maintained at the power supply voltage VDD in a stand-by state,the transistors MN142 is turned on, whereby the ground voltage VSS isapplied to the node N2.

FIG. 32 is a waveform diagram showing one example of the rewritingoperation using the rewriting circuit PRGM of FIG. 31. As shown in FIG.32, in the rewriting operation, a current in a direction in accordancewith the stored information can be supplied to the selected memory cell.More specifically, in the case of the set operation for writing thestored information ‘1’, when the set activation signal SETB which is atthe power supply voltage VDD is driven to the ground voltage VSS, thetransistors MP131 and MN141 are turned on, whereby a current can besupplied in a direction from the memory element RM to the transistor QMin the selected memory call. Contrary to this, in the case of the resetoperation for writing the stored information ‘0’, when the resetactivation signal RSTB which is at the power supply voltage VDD isdriven to the ground voltage VSS, the transistors MP141 and MN131 areturned on, whereby a current can be supplied in a direction from thetransistor QM to the memory element RM in the selected memory call.

Here, it is necessary to generate a larger Joule heat in the resetoperation than in the set operation. Also, since the memory element RMside becomes a source electrode, it is necessary to consider thesubstrate bias effect of the memory cell transistor. For this reason,the reset voltage VR is designed to be equal to the power supply voltageVDD, or it is designed to be lower than the power supply voltage VDD buthigher than the set voltage VS so that an absolute value of a resetcurrent is larger than that of a set current. In such a reset operation,similar to FIG. 29, a reset current (−IR) opposite in direction to theset current (IS) flows in the select memory cell MC11 even for a shortperiod. The absolute value of the reset current (|−IR|) is larger thanthe set current (IS).

In the foregoing, in the fifth embodiment described above, thesemiconductor device as shown in FIG. 30 and FIG. 31 is formed by usingthe memory element RM as described in the first embodiment and thesecond embodiment, so that a semiconductor device provided with high aheat-resistance property and a stable data retention property can berealized. Further, since a current is supplied by applying a voltage ina direction in accordance with the stored information in the rewritingoperation, segregation of indium ion can be prevented, and a more stabledata retention property can be realized.

More specifically, for example, since the bit line BL1L is applied withhigh voltage and the bit line BL1R is applied with low voltage in theset operation, electric field is generated in a direction from the upperelectrode 53 to the lower electrode TP of the memory element RM in FIG.4. Therefore, positive ions such as impacted-ionized indium areattracted to the vicinity of the lower electrode TP. Contrary to this,for example, since the bit line BL1R is applied with high voltage andthe bit line BL1L is applied with low voltage in the reset operation,electric field is generated in a direction from the lower electrode TPto the upper electrode 53 in FIG. 4. Therefore, a positively ionizedelement including an element such as indium is attracted in a directiontoward the upper electrode 53 along the line of electric force. On theother hand, positive ions may diffuse in an anode direction by thethermal diffusion caused by melting. By these means, localization of anelement due to the rewriting operation can be prevented, and therefore,the number of rewritable times can be improved. In other words, by theseeffects, a composition distribution in a film thickness direction in thepresent invention is stably maintained even if rewriting is repeatedmany times. Note that the composition distribution in which a metalelement such as In is much contained in the first layer can be stablymaintained by selecting a voltage polarity by which the upper electrode53 is turned to be positive in the set, in which thermal diffusion issmall and the ions relatively tend to be on one side of the filmthickness direction, and the upper electrode 53 is turned to be negativein the reset.

Also, when reverse voltage is applied in resetting from the set state asdescribed above (that is, the lower electrode TP side is turned to bepositive in the reset), since electrons are accelerated in an upperregion of aligned atomic arrangement and entered to the lower portion,it is advantage for increasing the temperature of the lower portion, andtherefore, an effect of reduction of the reset current can be alsoexpected. When high temperature in the reset state is maintained, thesecond layer in an upper portion in the film thickness direction iscrystallized, but since the full crystallization and further resistanceincrease are prevented in a region close to the lower electrode (thatis, the first layer and others), the heat-resistance property can bemaintained.

Note that, in the description above, a specification of a memory celltransistor is not particularly limited. However, it is also possible toboost the gate voltage by using a transistor having a thick gate oxidefilm as the memory cell transistor. By the configuration and operationas described above, the deterioration of driving capability of thememory cell transistor QM due to the substrate bias effect caused by thememory element RM can be suppressed, and a sufficient large resetcurrent can be supplied also in the direction reverse to conventionalone.

Sixth Embodiment

In a sixth embodiment, the configuration and operation in which thesemiconductor device of the fifth embodiment described above is modifiedwill be described. FIG. 33 is a circuit diagram showing a configurationexample of a semiconductor device according to the sixth embodiment ofthe present invention. The semiconductor device according to the sixthembodiment has a characteristic in its reading method, in which thedischarge circuit DCCKT shown in FIG. 30 is replaced by the pre-chargecircuit PCCKT as shown in FIG. 33 and source voltages of NMOStransistors MN1 to MNn and MN1R to MNnR in the pre-charge circuit PCCKTare set to a reading voltage VRD.

The reading operation in such a configuration is shown in FIG. 34. In astand-by state, the bit line pairs (BL1L and BL1R) to (BLnL and BLnR)are maintained at the reading voltage VRD by the pre-charge circuitPCCKT. When the reading activation signal RD which is at the groundvoltage VSS is driven to the power supply voltage VDD after theactivation of the column select line pair (YS1T and YS1B), the bit lineBL1R is discharged from the common data line CDR through the transistorMN112 in the reading circuit RC. Next, when the word line WL1 isactivated, a current path in the memory cell MC11 is formed, and areading signal in accordance with the stored information is inputted tothe sense amplifier SA from the bit line BL1L through the common dataline CDL and the transistor MN111 in the reading circuit RC. Aftersufficient reading signals are generated, the word line WL1 and thecolumn select line pair (YS1T and YS1B) are put into an inactive state,whereby the bit line pair (BL1L and BL1R) is driven to the readingvoltage VRD by the pre-charge circuit PCCKT. Lastly, the readingactivation signal RD which is at the power supply voltage VDD is drivento the ground voltage VSS, thereby returning to the stand-by state.

By the configuration and operation as described above, a reading timecan be shortened in addition to the effects described in the fifthembodiment. More specifically, for example, right after the generationof the reading signal, that is, right after the inactivation of thecolumn select line pair (YS1T and YS1B), a pre-charge operation of thebit line pair (BL1L and BL1R) can be performed in parallel with theoperation of the sense amplifier SA, and therefore, it is possible tosufficiently ensure the time assigned to the pre-charge operation. Also,since the bit line BL1R is discharged by using the NMOS transistor MN112in the reading circuit RC, a time for generating a potential differencein the bit line pair (BL1L and BL1R) can be shortened. Further, since itis not necessary to ensure the margin between the activation timing ofthe column select line pair (YS1L and YS1L) and the activation timing ofthe word line WL1, the select operation time of the memory cell MC11 canbe shortened. By the effects above, an access time and a cycle time inthe reading operation can be shortened, and therefore, a high-speedsemiconductor device (phase-change memory) can be realized.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

For example, as for the amorphous state and the crystalline statedescribed in the first embodiment, a whole region performing a memoryoperation is not required to be uniformly in these states, and a crystalgrain may exist inside the region of the amorphous state, or anamorphous part may exist inside the region of the crystalline state.More specifically, it is sufficient if changes between a state in whicha lot of amorphous portions are present and a state in which fewamorphous portions are present are caused and the resistance value isvaried therebetween.

Also, it can be understood from the film structure that the chalcogenidematerial (recording layer) with a composition described in the firstembodiment is a material in which crystallization accompanied with acrystal nucleation occurs instead of the crystal growth from theamorphous region. The chalcogenide material can be determined as amaterial in which crystallization accompanied with a crystal nucleationoccurs when the chalcogenide material layer is observed as three or moregranular pieces at a maximum in the film thickness direction, morepreferably six or more granular pieces at a maximum with scanningelectron microscope (SEM) or transmission electron microscope (TEM).Also, even if the material has a composition within a composition rangeof the present invention, the resistance change may occur therein inaddition to the phase change depending on the composition, due to theformation and disappearance of conductive paths made from a highconcentration region of metal or metalloid atoms or an atomic groupcontaining them moved by an electric field. More specifically, ifcrystal growth from outside to inside which becomes difficult by theaddition of indium (In) is not employed as a mechanism of a set, it isnot always necessary to employ only the phase-change by the crystalnucleation and the growth from the nucleus as the mechanism of the set.

INDUSTRIAL APPLICABILITY

A semiconductor integrated circuit device according to the presentinvention can be widely applied to a high-density integrated memorycircuit including a memory cell using a phase-change material or a logicembedded memory in which a memory circuit and a logic circuit areprovided on the same semiconductor substrate, and it becomes furtherbeneficial when such products are used under a high-temperaturecondition.

1. A semiconductor device comprising: a chalcogenide layer which recordsinformation by causing a change in an electrical resistance; an upperelectrode formed on an upper portion of the chalcogenide layer; and alower electrode formed on a lower portion of the chalcogenide layer,wherein the chalcogenide layer comprises at least two layers including afirst layer positioned on a lower electrode side and a second layerpositioned on an upper electrode side, an average content of a group IIor group III element of the first layer in a film thickness direction is7 atomic % or more and 40 atomic % or less, an average content of agroup II or group III element of the second layer in a film thicknessdirection is from 0% to 15 atomic % or less, and the average content ofthe first layer is 5 atomic % or more larger than the average content ofthe second layer, wherein the first layer is made of a materialcontaining: at least either indium (In) or gallium (Ga) of 7 atomic % ormore and 40 atomic % or less; germanium (Ge) of 5 atomic % or more and35 atomic % or less; antimony (Sb) of 5 atomic % or more and 25 atomic %or less; and tellurium (Te) of 40 atomic % or more and 65 atomic % orless.
 2. A semiconductor device comprising: a chalcogenide layer whichrecords information by causing a change in an electrical resistance; anupper electrode formed on an upper portion of the chalcogenide layer; alower electrode formed on a lower portion of the chalcogenide layer; abit line connected to the upper electrode; a transistor having one endconnected to the lower electrode and the other end connected to a groundvoltage; and a word line connected to a control terminal of thetransistor, wherein the chalcogenide layer comprises at least two layersincluding a first layer positioned on a lower electrode side and asecond layer positioned on an upper electrode side, an average contentof a group II or group III element of the first layer in a filmthickness direction is 7 atomic % or more and 40 atomic % or less, anaverage content of a group II or group III element of the second layerin a film thickness direction is from 0% to 15 atomic % or less, theaverage content of the first layer is 5 atomic % or more larger than theaverage content of the second layer, and a voltage higher than that ofthe lower electrode is applied to the upper electrode when informationis recorded in the chalcogenide layer, wherein the first layer is madeof a material containing: at least either indium (In) or gallium (Ga) of7 atomic % or more and 40 atomic % or less; germanium (Ge) of 5 atomic %or more and 35 atomic % or less; antimony (Sb) of 5 atomic % or more and25 atomic % or less; and tellurium (Te) of 40 atomic % or more and 65atomic % or less.